[PATCH 0/4] drm/i915: A few CHV stragglers

[PATCH 0/4] drm/i915: A few CHV stragglers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here are a few remaining CHV patches from the big series [1].
I reworked some of these a bit.

The remaining patches from the big series are all power sequencer related,
and I'm currently reworking those too. Will post them separately once I have
something decent.

[1] http://lists.freedesktop.org/archives/intel-gfx/2014-June/048132.html

Ville Syrjälä (4):
  drm/i915: Warn about odd rps values on CHV
  drm/i915: Populate mem_freq in init_gt_powerwave()
  drm/i915: Make sure hardware uses the correct swing margin/deemph bits
    on chv
  drm/i915: Clear TX FIFO reset master override bits on chv

 drivers/gpu/drm/i915/i915_reg.h   |  37 +++++++++++---
 drivers/gpu/drm/i915/intel_dp.c   |  23 +++++++++
 drivers/gpu/drm/i915/intel_hdmi.c |  23 +++++++++
 drivers/gpu/drm/i915/intel_pm.c   | 101 ++++++++++++++++++++------------------
 4 files changed, 131 insertions(+), 53 deletions(-)

-- 
1.8.5.5

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[PATCH 1/4] drm/i915: Warn about odd rps values on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV wants even rps opcodes so print a warning of the
min/max/rpe/rp1 values are odd, and warn if an odd value
slips through to valleyview_set_rps() and truncate it to
an even value.

Also add a comment to chv_freq_opcode() to make sure no one
changes the code without considering this requirement.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c8f744c..c84ad93 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3453,6 +3453,10 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
 			 dev_priv->rps.cur_freq,
 			 vlv_gpu_freq(dev_priv, val), val);
 
+	if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
+		      "Odd GPU freq value\n"))
+		val &= ~1;
+
 	if (val != dev_priv->rps.cur_freq)
 		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
 
@@ -4149,6 +4153,12 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
 			 dev_priv->rps.min_freq);
 
+	WARN_ONCE((dev_priv->rps.max_freq |
+		   dev_priv->rps.efficient_freq |
+		   dev_priv->rps.rp1_freq |
+		   dev_priv->rps.min_freq) & 1,
+		  "Odd GPU freq values\n");
+
 	/* Preserve min/max settings in case of re-init */
 	if (dev_priv->rps.max_freq_softlimit == 0)
 		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
@@ -7443,6 +7453,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 		return -1;
 	}
 
+	/* CHV needs even values */
 	opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
 
 	return opcode;
-- 
1.8.5.5

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[PATCH v2 2/4] drm/i915: Populate mem_freq in init_gt_powerwave()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

init_clock_gating() is too late to read out the mem_freq. We already
want to print out the GPU MHz numbers before it's called. Move the
mem_freq setup to init_gt_powersave().

v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  6 ---
 drivers/gpu/drm/i915/intel_pm.c | 90 ++++++++++++++++++++---------------------
 2 files changed, 43 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 203062e..2df946d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5650,12 +5650,6 @@ enum punit_power_well {
 						 GEN6_PM_RP_DOWN_THRESHOLD | \
 						 GEN6_PM_RP_DOWN_TIMEOUT)
 
-#define CHV_CZ_CLOCK_FREQ_MODE_200			200
-#define CHV_CZ_CLOCK_FREQ_MODE_267			267
-#define CHV_CZ_CLOCK_FREQ_MODE_320			320
-#define CHV_CZ_CLOCK_FREQ_MODE_333			333
-#define CHV_CZ_CLOCK_FREQ_MODE_400			400
-
 #define GEN7_GT_SCRATCH_BASE			0x4F100
 #define GEN7_GT_SCRATCH_REG_NUM			8
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c84ad93..39dd066 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4088,11 +4088,27 @@ static void valleyview_cleanup_pctx(struct drm_device *dev)
 static void valleyview_init_gt_powersave(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
 
 	valleyview_setup_pctx(dev);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+		dev_priv->mem_freq = 800;
+		break;
+	case 2:
+		dev_priv->mem_freq = 1066;
+		break;
+	case 3:
+		dev_priv->mem_freq = 1333;
+		break;
+	}
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
+
 	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
 	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
 	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
@@ -4127,11 +4143,38 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 static void cherryview_init_gt_powersave(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
 
 	cherryview_setup_pctx(dev);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
+	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
+	switch ((val >> 2) & 0x7) {
+	case 0:
+	case 1:
+		dev_priv->rps.cz_freq = 200;
+		dev_priv->mem_freq = 1600;
+		break;
+	case 2:
+		dev_priv->rps.cz_freq = 267;
+		dev_priv->mem_freq = 1600;
+		break;
+	case 3:
+		dev_priv->rps.cz_freq = 333;
+		dev_priv->mem_freq = 2000;
+		break;
+	case 4:
+		dev_priv->rps.cz_freq = 320;
+		dev_priv->mem_freq = 1600;
+		break;
+	case 5:
+		dev_priv->rps.cz_freq = 400;
+		dev_priv->mem_freq = 1600;
+		break;
+	}
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
+
 	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
 	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
 	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
@@ -5760,24 +5803,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 static void valleyview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val;
-
-	mutex_lock(&dev_priv->rps.hw_lock);
-	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-	mutex_unlock(&dev_priv->rps.hw_lock);
-	switch ((val >> 6) & 3) {
-	case 0:
-	case 1:
-		dev_priv->mem_freq = 800;
-		break;
-	case 2:
-		dev_priv->mem_freq = 1066;
-		break;
-	case 3:
-		dev_priv->mem_freq = 1333;
-		break;
-	}
-	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
@@ -5853,35 +5878,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val;
-
-	mutex_lock(&dev_priv->rps.hw_lock);
-	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
-	mutex_unlock(&dev_priv->rps.hw_lock);
-	switch ((val >> 2) & 0x7) {
-	case 0:
-	case 1:
-			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
-			dev_priv->mem_freq = 1600;
-			break;
-	case 2:
-			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
-			dev_priv->mem_freq = 1600;
-			break;
-	case 3:
-			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
-			dev_priv->mem_freq = 2000;
-			break;
-	case 4:
-			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
-			dev_priv->mem_freq = 1600;
-			break;
-	case 5:
-			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
-			dev_priv->mem_freq = 1600;
-			break;
-	}
-	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
-- 
1.8.5.5

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[PATCH 3/4] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The register can house two different swing marging/deemph settings at
once. However only one gets used based on some other bits. Make sure we
set those bits correctly to make the hardware use the settings we
provided.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 14 ++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2df946d..b8e8d33 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -824,12 +824,31 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW9_CH0		0x8224
 #define _VLV_PCS_DW9_CH1		0x8424
+#define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
+#define   DPIO_PCS_TX2MARGIN_000	(0<<13)
+#define   DPIO_PCS_TX2MARGIN_101	(1<<13)
+#define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
+#define   DPIO_PCS_TX1MARGIN_000	(0<<10)
+#define   DPIO_PCS_TX1MARGIN_101	(1<<10)
 #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
 
+#define _VLV_PCS01_DW9_CH0		0x224
+#define _VLV_PCS23_DW9_CH0		0x424
+#define _VLV_PCS01_DW9_CH1		0x2624
+#define _VLV_PCS23_DW9_CH1		0x2824
+#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
+#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
+
 #define _CHV_PCS_DW10_CH0		0x8228
 #define _CHV_PCS_DW10_CH1		0x8428
 #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
+#define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
+#define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
+#define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
+#define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
+#define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
+#define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
 
 #define _VLV_PCS01_DW10_CH0		0x0228
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e5ada4f..f8e4578 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2632,12 +2632,26 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	/* Clear calc init */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
+
 	/* Program swing deemph */
 	for (i = 0; i < 4; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9169786..f3bf0c7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1414,12 +1414,26 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	/* Clear calc init */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
+
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
 	for (i = 0; i < 4; i++) {
-- 
1.8.5.5

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[PATCH v2 4/4] drm/i915: Clear TX FIFO reset master override bits on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clear the override bits to make sure the hardware maanages
the TX FIFO reset master on its own.

v2: Squash with the earlier attempt at forcing the override bits

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   |  9 +++++++++
 drivers/gpu/drm/i915/intel_hdmi.c |  9 +++++++++
 3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8e8d33..daac02b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -784,6 +784,8 @@ enum punit_power_well {
 #define _VLV_PCS_DW0_CH1		0x8400
 #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
 #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
 
 #define _VLV_PCS01_DW0_CH0		0x200
@@ -860,8 +862,18 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW11_CH0		0x822c
 #define _VLV_PCS_DW11_CH1		0x842c
+#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
 
+#define _VLV_PCS01_DW11_CH0		0x022c
+#define _VLV_PCS23_DW11_CH0		0x042c
+#define _VLV_PCS01_DW11_CH1		0x262c
+#define _VLV_PCS23_DW11_CH1		0x282c
+#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
 #define _VLV_PCS_DW12_CH0		0x8230
 #define _VLV_PCS_DW12_CH1		0x8430
 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f8e4578..4f69648 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2223,6 +2223,15 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* allow hardware to manage TX FIFO reset source */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
 	/* Deassert soft data lane reset*/
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f3bf0c7..f0cff45 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1378,6 +1378,15 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* allow hardware to manage TX FIFO reset source */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
 	/* Deassert soft data lane reset*/
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
-- 
1.8.5.5

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Re: [PATCH 1/4] drm/i915: Warn about odd rps values on CHV

[Deepak S]

On Monday 18 August 2014 05:12 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV wants even rps opcodes so print a warning of the
> min/max/rpe/rp1 values are odd, and warn if an odd value
> slips through to valleyview_set_rps() and truncate it to
> an even value.
>
> Also add a comment to chv_freq_opcode() to make sure no one
> changes the code without considering this requirement.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>   1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c8f744c..c84ad93 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3453,6 +3453,10 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
>   			 dev_priv->rps.cur_freq,
>   			 vlv_gpu_freq(dev_priv, val), val);
>   
> +	if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
> +		      "Odd GPU freq value\n"))
> +		val &= ~1;
> +
>   	if (val != dev_priv->rps.cur_freq)
>   		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
>   
> @@ -4149,6 +4153,12 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>   			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>   			 dev_priv->rps.min_freq);
>   
> +	WARN_ONCE((dev_priv->rps.max_freq |
> +		   dev_priv->rps.efficient_freq |
> +		   dev_priv->rps.rp1_freq |
> +		   dev_priv->rps.min_freq) & 1,
> +		  "Odd GPU freq values\n");
> +
>   	/* Preserve min/max settings in case of re-init */
>   	if (dev_priv->rps.max_freq_softlimit == 0)
>   		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
> @@ -7443,6 +7453,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>   		return -1;
>   	}
>   
> +	/* CHV needs even values */
>   	opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
>   
>   	return opcode;

Patch looks fine to me
Reviewed-by: Deepak S <deepak.s@linux.intel.com>

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Re: [PATCH v2 2/4] drm/i915: Populate mem_freq in init_gt_powerwave()

[Deepak S]

On Monday 18 August 2014 05:12 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> init_clock_gating() is too late to read out the mem_freq. We already
> want to print out the GPU MHz numbers before it's called. Move the
> mem_freq setup to init_gt_powersave().
>
> v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h |  6 ---
>   drivers/gpu/drm/i915/intel_pm.c | 90 ++++++++++++++++++++---------------------
>   2 files changed, 43 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 203062e..2df946d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5650,12 +5650,6 @@ enum punit_power_well {
>   						 GEN6_PM_RP_DOWN_THRESHOLD | \
>   						 GEN6_PM_RP_DOWN_TIMEOUT)
>   
> -#define CHV_CZ_CLOCK_FREQ_MODE_200			200
> -#define CHV_CZ_CLOCK_FREQ_MODE_267			267
> -#define CHV_CZ_CLOCK_FREQ_MODE_320			320
> -#define CHV_CZ_CLOCK_FREQ_MODE_333			333
> -#define CHV_CZ_CLOCK_FREQ_MODE_400			400
> -
>   #define GEN7_GT_SCRATCH_BASE			0x4F100
>   #define GEN7_GT_SCRATCH_REG_NUM			8
>   
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c84ad93..39dd066 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4088,11 +4088,27 @@ static void valleyview_cleanup_pctx(struct drm_device *dev)
>   static void valleyview_init_gt_powersave(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
>   
>   	valleyview_setup_pctx(dev);
>   
>   	mutex_lock(&dev_priv->rps.hw_lock);
>   
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +		dev_priv->mem_freq = 800;
> +		break;
> +	case 2:
> +		dev_priv->mem_freq = 1066;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 1333;
> +		break;
> +	}
> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
> +
>   	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
>   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> @@ -4127,11 +4143,38 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>   static void cherryview_init_gt_powersave(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
>   
>   	cherryview_setup_pctx(dev);
>   
>   	mutex_lock(&dev_priv->rps.hw_lock);
>   
> +	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
> +	switch ((val >> 2) & 0x7) {
> +	case 0:
> +	case 1:
> +		dev_priv->rps.cz_freq = 200;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 2:
> +		dev_priv->rps.cz_freq = 267;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 3:
> +		dev_priv->rps.cz_freq = 333;
> +		dev_priv->mem_freq = 2000;
> +		break;
> +	case 4:
> +		dev_priv->rps.cz_freq = 320;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 5:
> +		dev_priv->rps.cz_freq = 400;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	}
> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
> +
>   	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
>   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> @@ -5760,24 +5803,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>   static void valleyview_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->rps.hw_lock);
> -	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -	mutex_unlock(&dev_priv->rps.hw_lock);
> -	switch ((val >> 6) & 3) {
> -	case 0:
> -	case 1:
> -		dev_priv->mem_freq = 800;
> -		break;
> -	case 2:
> -		dev_priv->mem_freq = 1066;
> -		break;
> -	case 3:
> -		dev_priv->mem_freq = 1333;
> -		break;
> -	}
> -	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>   
>   	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>   
> @@ -5853,35 +5878,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>   static void cherryview_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->rps.hw_lock);
> -	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
> -	mutex_unlock(&dev_priv->rps.hw_lock);
> -	switch ((val >> 2) & 0x7) {
> -	case 0:
> -	case 1:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	case 2:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	case 3:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
> -			dev_priv->mem_freq = 2000;
> -			break;
> -	case 4:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	case 5:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	}
> -	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>   
>   	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>   

Patch looks fine to me
Reviewed-by: Deepak S<deepak.s@linux.intel.com>


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Re: [PATCH 3/4] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The register can house two different swing marging/deemph settings at
> once. However only one gets used based on some other bits. Make sure we
> set those bits correctly to make the hardware use the settings we
> provided.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c | 14 ++++++++++++++
>  3 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2df946d..b8e8d33 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -824,12 +824,31 @@ enum punit_power_well {
>  
>  #define _VLV_PCS_DW9_CH0		0x8224
>  #define _VLV_PCS_DW9_CH1		0x8424
> +#define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
> +#define   DPIO_PCS_TX2MARGIN_000	(0<<13)
> +#define   DPIO_PCS_TX2MARGIN_101	(1<<13)
> +#define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
> +#define   DPIO_PCS_TX1MARGIN_000	(0<<10)
> +#define   DPIO_PCS_TX1MARGIN_101	(1<<10)
>  #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
>  
> +#define _VLV_PCS01_DW9_CH0		0x224
> +#define _VLV_PCS23_DW9_CH0		0x424
> +#define _VLV_PCS01_DW9_CH1		0x2624
> +#define _VLV_PCS23_DW9_CH1		0x2824
> +#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
> +#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
> +
>  #define _CHV_PCS_DW10_CH0		0x8228
>  #define _CHV_PCS_DW10_CH1		0x8428
>  #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
>  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
> +#define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
> +#define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
> +#define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
> +#define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
> +#define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
> +#define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
>  #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
>  
>  #define _VLV_PCS01_DW10_CH0		0x0228
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e5ada4f..f8e4578 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2632,12 +2632,26 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	/* Clear calc init */
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
>  
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> +
>  	/* Program swing deemph */
>  	for (i = 0; i < 4; i++) {
>  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9169786..f3bf0c7 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1414,12 +1414,26 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	/* Clear calc init */
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
>  
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> +
>  	/* FIXME: Program the support xxx V-dB */
>  	/* Use 800mV-0dB */
>  	for (i = 0; i < 4; i++) {
> -- 
> 1.8.5.5
>
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Re: [PATCH v2 4/4] drm/i915: Clear TX FIFO reset master override bits on chv

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clear the override bits to make sure the hardware maanages
> the TX FIFO reset master on its own.
>
> v2: Squash with the earlier attempt at forcing the override bits
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c   |  9 +++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c |  9 +++++++++
>  3 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b8e8d33..daac02b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -784,6 +784,8 @@ enum punit_power_well {
>  #define _VLV_PCS_DW0_CH1		0x8400
>  #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
>  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
>  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>  
>  #define _VLV_PCS01_DW0_CH0		0x200
> @@ -860,8 +862,18 @@ enum punit_power_well {
>  
>  #define _VLV_PCS_DW11_CH0		0x822c
>  #define _VLV_PCS_DW11_CH1		0x842c
> +#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
>  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
>  
> +#define _VLV_PCS01_DW11_CH0		0x022c
> +#define _VLV_PCS23_DW11_CH0		0x042c
> +#define _VLV_PCS01_DW11_CH1		0x262c
> +#define _VLV_PCS23_DW11_CH1		0x282c
> +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> +
>  #define _VLV_PCS_DW12_CH0		0x8230
>  #define _VLV_PCS_DW12_CH1		0x8430
>  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f8e4578..4f69648 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2223,6 +2223,15 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> +	/* allow hardware to manage TX FIFO reset source */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +
>  	/* Deassert soft data lane reset*/
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f3bf0c7..f0cff45 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1378,6 +1378,15 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> +	/* allow hardware to manage TX FIFO reset source */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +
>  	/* Deassert soft data lane reset*/
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -- 
> 1.8.5.5
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2 4/4] drm/i915: Clear TX FIFO reset master override bits on chv

[Daniel Vetter]

On Thu, Oct 02, 2014 at 05:33:05PM +0300, Mika Kuoppala wrote:
> ville.syrjala@linux.intel.com writes:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Clear the override bits to make sure the hardware maanages
> > the TX FIFO reset master on its own.
> >
> > v2: Squash with the earlier attempt at forcing the override bits
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Remaining two patches from this series merged, thanks.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
> >  drivers/gpu/drm/i915/intel_dp.c   |  9 +++++++++
> >  drivers/gpu/drm/i915/intel_hdmi.c |  9 +++++++++
> >  3 files changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b8e8d33..daac02b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -784,6 +784,8 @@ enum punit_power_well {
> >  #define _VLV_PCS_DW0_CH1		0x8400
> >  #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
> >  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
> >  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> >  
> >  #define _VLV_PCS01_DW0_CH0		0x200
> > @@ -860,8 +862,18 @@ enum punit_power_well {
> >  
> >  #define _VLV_PCS_DW11_CH0		0x822c
> >  #define _VLV_PCS_DW11_CH1		0x842c
> > +#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
> >  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> >  
> > +#define _VLV_PCS01_DW11_CH0		0x022c
> > +#define _VLV_PCS23_DW11_CH0		0x042c
> > +#define _VLV_PCS01_DW11_CH1		0x262c
> > +#define _VLV_PCS23_DW11_CH1		0x282c
> > +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> > +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> > +
> >  #define _VLV_PCS_DW12_CH0		0x8230
> >  #define _VLV_PCS_DW12_CH1		0x8430
> >  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f8e4578..4f69648 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2223,6 +2223,15 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
> >  
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> > +	/* allow hardware to manage TX FIFO reset source */
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> > +
> >  	/* Deassert soft data lane reset*/
> >  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index f3bf0c7..f0cff45 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1378,6 +1378,15 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> >  
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> > +	/* allow hardware to manage TX FIFO reset source */
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> > +
> >  	/* Deassert soft data lane reset*/
> >  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > -- 
> > 1.8.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch