From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV Date: Fri, 11 Jul 2014 18:03:16 +0300 Message-ID: <87d2dcj5u3.fsf@gaia.fi.intel.com> References: <1404978387-28180-1-git-send-email-deepak.s@linux.intel.com> <1404978387-28180-7-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 8942D6E849 for ; Fri, 11 Jul 2014 08:03:45 -0700 (PDT) In-Reply-To: <1404978387-28180-7-git-send-email-deepak.s@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org deepak.s@linux.intel.com writes: > From: Deepak S > > Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same for CHV. > > Signed-off-by: Deepak S Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_irq.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 38e6de1..ae6246c 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1403,7 +1403,7 @@ static void gen6_pm_rps_work(struct work_struct *work) > spin_lock_irq(&dev_priv->irq_lock); > pm_iir = dev_priv->rps.pm_iir; > dev_priv->rps.pm_iir = 0; > - if (IS_BROADWELL(dev_priv->dev)) > + if (IS_BROADWELL(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev)) > bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > else { > /* Make sure not to corrupt PMIMR state used by ringbuffer */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6abd05b..7da3719 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3398,6 +3398,8 @@ static void cherryview_disable_rps(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > I915_WRITE(GEN6_RC_CONTROL, 0); > + > + gen8_disable_rps_interrupts(dev); > } > > static void valleyview_disable_rps(struct drm_device *dev) > @@ -4115,6 +4117,8 @@ static void cherryview_enable_rps(struct drm_device *dev) > > valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); > > + gen8_enable_rps_interrupts(dev); > + > gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > } > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx