* [PATCH] drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX
@ 2014-04-29 14:00 Paulo Zanoni
2014-04-29 14:08 ` Daniel Vetter
2014-04-29 21:43 ` Dave Airlie
0 siblings, 2 replies; 4+ messages in thread
From: Paulo Zanoni @ 2014-04-29 14:00 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Because the docs say ULX doesn't support it on HSW.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_dp.c | 3 ++-
include/drm/i915_pciids.h | 4 ++--
3 files changed, 7 insertions(+), 3 deletions(-)
This patch is completely untested!!!
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e81feab..bdc612c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1816,6 +1816,9 @@ struct drm_i915_cmd_table {
#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
((dev)->pdev->device & 0x00F0) == 0x0020)
+/* ULX machines are also considered ULT. */
+#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
+ (dev)->pdev->device == 0x0A1E)
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
/*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 34ed143..87b0a51 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
case DP_LINK_BW_2_7:
break;
case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
- if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
+ if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
+ INTEL_INFO(dev)->gen >= 8) &&
intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
max_link_bw = DP_LINK_BW_5_4;
else
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 24f3cad..5cd9165 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -191,8 +191,8 @@
INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
--
1.9.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX
2014-04-29 14:00 [PATCH] drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX Paulo Zanoni
@ 2014-04-29 14:08 ` Daniel Vetter
2014-04-29 21:43 ` Dave Airlie
1 sibling, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2014-04-29 14:08 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
Todd, can you please quickly review this one?
Thanks, Daniel
On Tue, Apr 29, 2014 at 4:00 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Because the docs say ULX doesn't support it on HSW.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_dp.c | 3 ++-
> include/drm/i915_pciids.h | 4 ++--
> 3 files changed, 7 insertions(+), 3 deletions(-)
>
>
> This patch is completely untested!!!
>
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e81feab..bdc612c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1816,6 +1816,9 @@ struct drm_i915_cmd_table {
> #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
> #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
> ((dev)->pdev->device & 0x00F0) == 0x0020)
> +/* ULX machines are also considered ULT. */
> +#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
> + (dev)->pdev->device == 0x0A1E)
> #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 34ed143..87b0a51 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
> case DP_LINK_BW_2_7:
> break;
> case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
> - if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
> + if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> + INTEL_INFO(dev)->gen >= 8) &&
> intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
> max_link_bw = DP_LINK_BW_5_4;
> else
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 24f3cad..5cd9165 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -191,8 +191,8 @@
> INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> --
> 1.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX
2014-04-29 14:00 [PATCH] drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX Paulo Zanoni
2014-04-29 14:08 ` Daniel Vetter
@ 2014-04-29 21:43 ` Dave Airlie
2014-04-30 6:55 ` Jani Nikula
1 sibling, 1 reply; 4+ messages in thread
From: Dave Airlie @ 2014-04-29 21:43 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni
On 30 April 2014 00:00, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Because the docs say ULX doesn't support it on HSW.
i read the exact same thing,
Reviewed-by: Dave Airlie <airlied@redhat.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_dp.c | 3 ++-
> include/drm/i915_pciids.h | 4 ++--
> 3 files changed, 7 insertions(+), 3 deletions(-)
>
>
> This patch is completely untested!!!
>
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e81feab..bdc612c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1816,6 +1816,9 @@ struct drm_i915_cmd_table {
> #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
> #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
> ((dev)->pdev->device & 0x00F0) == 0x0020)
> +/* ULX machines are also considered ULT. */
> +#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
> + (dev)->pdev->device == 0x0A1E)
> #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 34ed143..87b0a51 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
> case DP_LINK_BW_2_7:
> break;
> case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
> - if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
> + if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> + INTEL_INFO(dev)->gen >= 8) &&
> intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
> max_link_bw = DP_LINK_BW_5_4;
> else
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 24f3cad..5cd9165 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -191,8 +191,8 @@
> INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> --
> 1.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX
2014-04-29 21:43 ` Dave Airlie
@ 2014-04-30 6:55 ` Jani Nikula
0 siblings, 0 replies; 4+ messages in thread
From: Jani Nikula @ 2014-04-30 6:55 UTC (permalink / raw)
To: Dave Airlie, Paulo Zanoni; +Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni
On Wed, 30 Apr 2014, Dave Airlie <airlied@gmail.com> wrote:
> On 30 April 2014 00:00, Paulo Zanoni <przanoni@gmail.com> wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> Because the docs say ULX doesn't support it on HSW.
>
> i read the exact same thing,
>
> Reviewed-by: Dave Airlie <airlied@redhat.com>
Pushed to -fixes, thanks for the patch and review.
BR,
Jani.
>
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 3 +++
>> drivers/gpu/drm/i915/intel_dp.c | 3 ++-
>> include/drm/i915_pciids.h | 4 ++--
>> 3 files changed, 7 insertions(+), 3 deletions(-)
>>
>>
>> This patch is completely untested!!!
>>
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index e81feab..bdc612c 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1816,6 +1816,9 @@ struct drm_i915_cmd_table {
>> #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
>> #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
>> ((dev)->pdev->device & 0x00F0) == 0x0020)
>> +/* ULX machines are also considered ULT. */
>> +#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
>> + (dev)->pdev->device == 0x0A1E)
>> #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
>>
>> /*
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 34ed143..87b0a51 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
>> case DP_LINK_BW_2_7:
>> break;
>> case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
>> - if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
>> + if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>> + INTEL_INFO(dev)->gen >= 8) &&
>> intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
>> max_link_bw = DP_LINK_BW_5_4;
>> else
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 24f3cad..5cd9165 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -191,8 +191,8 @@
>> INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
>> INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
>> INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
>> - INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
>> - INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
>> + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
>> + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
>> INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
>> INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
>> INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
>> --
>> 1.9.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-04-30 6:55 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2014-04-29 14:00 [PATCH] drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX Paulo Zanoni
2014-04-29 14:08 ` Daniel Vetter
2014-04-29 21:43 ` Dave Airlie
2014-04-30 6:55 ` Jani Nikula
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