From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1899EC18E5B for ; Tue, 17 Mar 2020 00:07:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E601F206C0 for ; Tue, 17 Mar 2020 00:07:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E601F206C0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C6CA6E511; Tue, 17 Mar 2020 00:07:45 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 51A796E511 for ; Tue, 17 Mar 2020 00:07:44 +0000 (UTC) IronPort-SDR: olUGO+U6IJk+oxiMTlFvIKARbBFbk2/sWmB4AjKdP0hCHbgBlh5remr8/rBcwJ2VzCY2BICxJd XKl53iaikphw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2020 17:07:43 -0700 IronPort-SDR: yHJBUrqNqYKGshvO3d7vrITKoN1RxBYiAAEtNV7QpONCClxnaz9M3NmAqWZ6rHW3jbvi9QbPBb 0CtZe+RBRBqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,562,1574150400"; d="scan'208";a="247645461" Received: from unknown (HELO adixit-arch.intel.com) ([10.134.76.164]) by orsmga006.jf.intel.com with ESMTP; 16 Mar 2020 17:07:43 -0700 Date: Mon, 16 Mar 2020 17:02:42 -0700 Message-ID: <87eetrn90d.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20200312230502.36898-5-umesh.nerlige.ramappa@intel.com> References: <20200312230502.36898-1-umesh.nerlige.ramappa@intel.com> <20200312230502.36898-5-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/perf: add new open param to configure polling of OA buffer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 12 Mar 2020 16:05:02 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin > > This new parameter let's the application choose how often the OA > buffer should be checked on the CPU side for data availability. Longer > polling period tend to reduce CPU overhead if the application does not > care about somewhat real time data collection. Lionely already has comments on this so skipping those. > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 21a63644846f..ca139ac31b11 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -262,11 +262,11 @@ > */ > #define OA_TAIL_MARGIN_NSEC 100000ULL > > -/* frequency for checking whether the OA unit has written new reports to the > - * circular OA buffer... > +/* The default frequency for checking whether the OA unit has written new > + * reports to the circular OA buffer... > */ > -#define POLL_FREQUENCY 200 > -#define POLL_PERIOD (NSEC_PER_SEC / POLL_FREQUENCY) > +#define DEFAULT_POLL_FREQUENCY 200 > +#define DEFAULT_POLL_PERIOD (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY) nit, but I mostly like to have "units" as part of the name, so I'd recommed calling this DEFAULT_POLL_PERIOD_NS. > @@ -349,6 +349,8 @@ static const struct i915_oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = { > * @oa_periodic: Whether to enable periodic OA unit sampling > * @oa_period_exponent: The OA unit sampling period is derived from this > * @engine: The engine (typically rcs0) being monitored by the OA unit > + * @poll_oa_period: The period at which the CPU will check for OA data > + * availability > * > * As read_properties_unlocked() enumerates and validates the properties given > * to open a stream of metrics the configuration is built up in the structure > @@ -368,6 +370,7 @@ struct perf_open_properties { > int oa_period_exponent; > > struct intel_engine_cs *engine; > + u64 poll_oa_period; poll_oa_period_ns? > @@ -2642,9 +2645,9 @@ static void i915_oa_stream_enable(struct i915_perf_stream *stream) > > stream->perf->ops.oa_enable(stream); > > - if (stream->periodic) > + if (stream->periodic && stream->poll_oa_period) poll_oa_period check is not required, it's always present. > @@ -3617,6 +3625,14 @@ static int read_properties_unlocked(struct i915_perf *perf, > case DRM_I915_PERF_PROP_HOLD_PREEMPTION: > props->hold_preemption = !!value; > break; > + case DRM_I915_PERF_PROP_POLL_OA_DELAY: > + if (value < 100000 /* 100us */) { So no maximum? That's probably ok, reap what you sow. Have we tested 100 us, seems low, anyway. > diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h > index 9ee7c58e70d5..01559ead22e2 100644 > --- a/drivers/gpu/drm/i915/i915_perf_types.h > +++ b/drivers/gpu/drm/i915/i915_perf_types.h > @@ -304,6 +304,12 @@ struct i915_perf_stream { > * reprogrammed. > */ > struct i915_vma *noa_wait; > + > + /** > + * @poll_oa_period: The period in nanoseconds at which the OA > + * buffer should be checked for available data. > + */ > + u64 poll_oa_period; poll_oa_period_ns? > }; > > /** > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index 2813e579b480..dd511e7f795d 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -1969,6 +1969,19 @@ enum drm_i915_perf_property_id { > */ > DRM_I915_PERF_PROP_HOLD_PREEMPTION, > > + /** > + * This optional parameter specifies the timer interval in nanoseconds > + * at which the i915 driver will check the OA buffer for available data. > + * Minimum allowed value is 100 microseconds. A default value is used by > + * the driver if this parameter is not specified. Note that a large > + * value may reduce cpu consumption during OA perf captures, but it > + * would also potentially result in OA buffer overwrite as the captures > + * reach end of the OA buffer. > + * > + * This property is available in perf revision 4. > + */ > + DRM_I915_PERF_PROP_POLL_OA_DELAY, Is DRM_I915_PERF_PROP_POLL_OA_PERIOD_NS a better name? At least PERIOD instead of DELAY. Thanks! -- Ashutosh _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx