From: Jani Nikula <jani.nikula@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [RFC 0/3] Display uncore
Date: Thu, 08 Aug 2019 16:58:37 +0300 [thread overview]
Message-ID: <87ef1viws2.fsf@intel.com> (raw)
In-Reply-To: <156527094392.21710.16070553711212669704@skylake-alporthouse-com>
On Thu, 08 Aug 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Daniele Ceraolo Spurio (2019-08-08 02:44:20)
>> I've been trying to identify MMIO ranges to clearly define what belongs
>> to display_uncore to do a check on access, but there are lots of
>> exceptions and differences across gens (with a few more coming with TGL),
>> so I don't think that's a viable way. The alternative option implemented
>> here is to differentiate the register by type, which should ensure we
>> never mix them up, but at the cost of a more complex transition.
>
> One thing we could try with this approach is to tag every _MMIO() as
> either DE or GT and have the uncore accessors check the magic bits
> before scrubbing them. (With enough magic macros to make it disappear
>
> Huge task, but not insurmountable. The danger is that if we do this
> piecemeal is that we may end up with two simultaneous accesses via the
> separate uncore accessors. Hmm.
You mean something like this?
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b362ca0663a6..401490f79935 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -179,7 +179,8 @@
#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
typedef struct {
- u32 reg;
+ u32 de:1;
+ u32 reg:31;
} i915_reg_t;
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
---
bloat-o-meter tells me just that, with no other changes is +0.53%
increase. Perhaps still acceptable.
I think we could just add something like
#define _MMIO_DE(r) ((const i915_reg_t){ .de = 1, .reg = (r) })
and update i915_reg.h to use that as the first step, with no other
changes, and build on top of that. I don't think there should be large
scale changes outside of i915_reg.h required at all at first. The update
to move away from I915_READ and I915_WRITE could come afterwards and
piecemeal AFAICT.
> On thing though is that Jani may find the intel_de_write (or just
> de_write, the frequency may be worth bending the naming rules) as being
> palatable.
Indeed. Already intel_de_write(i915, ...) is so much better than
intel_uncore_write(&i915->uncore, ...).
Though... with de encoded in i915_reg_t, we could have intel_write(i915,
...) do the right thing based on .de. It could internally choose the
right uncore for intel_uncore_write(). Even if most non-de would
directly use the uncore versions.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-08-08 13:54 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-08 1:44 [RFC 0/3] Display uncore Daniele Ceraolo Spurio
2019-08-08 1:44 ` [RFC 1/3] drm/i915: split out uncore_mmio_debug Daniele Ceraolo Spurio
2019-08-08 13:08 ` Mika Kuoppala
2019-08-08 16:43 ` Daniele Ceraolo Spurio
2019-08-08 16:59 ` Chris Wilson
2019-08-08 1:44 ` [RFC 2/3] drm/i915: introduce display_uncore Daniele Ceraolo Spurio
2019-08-08 1:44 ` [RFC 3/3] drm/i915: convert a couple of registers to _DE_MMIO Daniele Ceraolo Spurio
2019-08-08 2:05 ` ✗ Fi.CI.CHECKPATCH: warning for Display uncore (rev3) Patchwork
2019-08-08 2:07 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-08 2:27 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-08 13:29 ` [RFC 0/3] Display uncore Chris Wilson
2019-08-08 13:58 ` Jani Nikula [this message]
2019-08-08 16:47 ` Daniele Ceraolo Spurio
2019-08-08 17:13 ` Lucas De Marchi
2019-08-09 7:58 ` Jani Nikula
2019-08-08 14:40 ` ✗ Fi.CI.IGT: failure for Display uncore (rev3) Patchwork
2019-10-29 9:23 ` [RFC 0/3] Display uncore Jani Nikula
2019-10-29 9:23 ` [Intel-gfx] " Jani Nikula
2019-10-29 21:18 ` Daniele Ceraolo Spurio
2019-10-29 21:18 ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-30 6:11 ` Jani Nikula
2019-10-30 6:11 ` [Intel-gfx] " Jani Nikula
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87ef1viws2.fsf@intel.com \
--to=jani.nikula@intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=daniele.ceraolospurio@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).