[PATCH v7 00/23] drm/i915/icl: dsi enabling

[PATCH v7 00/23] drm/i915/icl: dsi enabling

[Jani Nikula]

The v7 is a bit misleading, but it's essentially the next version of
[1], embedding my review into the commits directly. This is the first
batch from me, and there's more to come.

The new patches that I've added naturally need review.

The patches I've changed need approval from Madhav. I think two sets of
eyballs should be enough, and an additional independent review is
redundant (though of course appreciated).

The patches I've not changed I think can be pushed as-is, as long as the
dependencies have been merged appropriately.

BR,
Jani.


[1] http://mid.mail-archive.com/1537095223-5184-1-git-send-email-madhav.chauhan@intel.com


Jani Nikula (4):
  drm/i915: make encoder enable and disable hooks optional
  drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
  drm/i915/dsi: abstract dphy parameter init
  drm/i915/dsi: abstract intel_dsi_tlpx_ns()

Madhav Chauhan (19):
  drm/i915/icl: Make common DSI functions available
  drm/i915/icl: Program DSI clock and data lane timing params
  drm/i915/icl: Program TA_TIMING_PARAM registers
  drm/i915/icl: Get DSI transcoder for a given port
  drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  drm/i915/icl: Configure DSI transcoders
  drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
  drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
  drm/i915/icl: Define DSI transcoder timing registers
  drm/i915/icl: Configure DSI transcoder timings
  drm/i915/icl: Define TRANS_CONF register for DSI
  drm/i915/icl: Enable DSI transcoders
  drm/i915/icl: Define DSI panel programming registers
  drm/i915/icl: Set max return packet size for DSI panel
  drm/i915/icl: Power on DSI panel
  drm/i915/icl: Wait for header/payload credits release
  drm/i915/icl: Ensure all cmd/data disptached to panel
  drm/i915/icl: Turn ON panel backlight

 drivers/gpu/drm/i915/Makefile        |   1 +
 drivers/gpu/drm/i915/i915_pci.c      |   6 +
 drivers/gpu/drm/i915/i915_reg.h      | 126 ++++++++++
 drivers/gpu/drm/i915/icl_dsi.c       | 443 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c |   6 +-
 drivers/gpu/drm/i915/intel_display.h |   6 +-
 drivers/gpu/drm/i915/intel_dsi.c     |  30 +++
 drivers/gpu/drm/i915/intel_dsi.h     |  21 ++
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 279 +++++++++++++++-------
 drivers/gpu/drm/i915/vlv_dsi.c       |  37 +--
 10 files changed, 830 insertions(+), 125 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi.c

-- 
2.11.0

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[PATCH v7 01/23] drm/i915: make encoder enable and disable hooks optional

[Jani Nikula]

Encoders are not alike, make enable and disable hooks optional like
other hooks. Utilize this in DSI code, and remove the silly nop hook.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  6 ++++--
 drivers/gpu/drm/i915/vlv_dsi.c       | 16 ++++------------
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 41abd03ce6a6..32ea71bac663 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5461,7 +5461,8 @@ static void intel_encoders_enable(struct drm_crtc *crtc,
 		if (conn_state->crtc != crtc)
 			continue;
 
-		encoder->enable(encoder, crtc_state, conn_state);
+		if (encoder->enable)
+			encoder->enable(encoder, crtc_state, conn_state);
 		intel_opregion_notify_encoder(encoder, true);
 	}
 }
@@ -5482,7 +5483,8 @@ static void intel_encoders_disable(struct drm_crtc *crtc,
 			continue;
 
 		intel_opregion_notify_encoder(encoder, false);
-		encoder->disable(encoder, old_crtc_state, old_conn_state);
+		if (encoder->disable)
+			encoder->disable(encoder, old_crtc_state, old_conn_state);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index bafeb2a19b90..dbca30460a6b 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -794,6 +794,10 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
  * - wait t4                                           - wait t4
  */
 
+/*
+ * DSI port enable has to be done before pipe and plane enable, so we do it in
+ * the pre_enable hook instead of the enable hook.
+ */
 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *pipe_config,
 				 const struct drm_connector_state *conn_state)
@@ -896,17 +900,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 }
 
 /*
- * DSI port enable has to be done before pipe and plane enable, so we do it in
- * the pre_enable hook.
- */
-static void intel_dsi_enable_nop(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *pipe_config,
-				 const struct drm_connector_state *conn_state)
-{
-	DRM_DEBUG_KMS("\n");
-}
-
-/*
  * DSI port disable has to be done after pipe and plane disable, so we do it in
  * the post_disable hook.
  */
@@ -1764,7 +1757,6 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 
 	intel_encoder->compute_config = intel_dsi_compute_config;
 	intel_encoder->pre_enable = intel_dsi_pre_enable;
-	intel_encoder->enable = intel_dsi_enable_nop;
 	intel_encoder->disable = intel_dsi_disable;
 	intel_encoder->post_disable = intel_dsi_post_disable;
 	intel_encoder->get_hw_state = intel_dsi_get_hw_state;
-- 
2.11.0

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Re: [PATCH v7 01/23] drm/i915: make encoder enable and disable hooks optional

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> Encoders are not alike, make enable and disable hooks optional like
> other hooks. Utilize this in DSI code, and remove the silly nop hook.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c |  6 ++++--
>   drivers/gpu/drm/i915/vlv_dsi.c       | 16 ++++------------
>   2 files changed, 8 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 41abd03ce6a6..32ea71bac663 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5461,7 +5461,8 @@ static void intel_encoders_enable(struct drm_crtc *crtc,
>   		if (conn_state->crtc != crtc)
>   			continue;
>   
> -		encoder->enable(encoder, crtc_state, conn_state);
> +		if (encoder->enable)
> +			encoder->enable(encoder, crtc_state, conn_state);
>   		intel_opregion_notify_encoder(encoder, true);
>   	}
>   }
> @@ -5482,7 +5483,8 @@ static void intel_encoders_disable(struct drm_crtc *crtc,
>   			continue;
>   
>   		intel_opregion_notify_encoder(encoder, false);
> -		encoder->disable(encoder, old_crtc_state, old_conn_state);
> +		if (encoder->disable)
> +			encoder->disable(encoder, old_crtc_state, old_conn_state);
>   	}

encoder->disable() gets called directly inside intel_sanitize_encoder() 
without

intel_encoders_disable().I think, we need to put the check there as well.


With that fix,
Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>

Regards,
Madhav

>   }
>   
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index bafeb2a19b90..dbca30460a6b 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -794,6 +794,10 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>    * - wait t4                                           - wait t4
>    */
>   
> +/*
> + * DSI port enable has to be done before pipe and plane enable, so we do it in
> + * the pre_enable hook instead of the enable hook.
> + */
>   static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>   				 const struct intel_crtc_state *pipe_config,
>   				 const struct drm_connector_state *conn_state)
> @@ -896,17 +900,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>   }
>   
>   /*
> - * DSI port enable has to be done before pipe and plane enable, so we do it in
> - * the pre_enable hook.
> - */
> -static void intel_dsi_enable_nop(struct intel_encoder *encoder,
> -				 const struct intel_crtc_state *pipe_config,
> -				 const struct drm_connector_state *conn_state)
> -{
> -	DRM_DEBUG_KMS("\n");
> -}
> -
> -/*
>    * DSI port disable has to be done after pipe and plane disable, so we do it in
>    * the post_disable hook.
>    */
> @@ -1764,7 +1757,6 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
>   
>   	intel_encoder->compute_config = intel_dsi_compute_config;
>   	intel_encoder->pre_enable = intel_dsi_pre_enable;
> -	intel_encoder->enable = intel_dsi_enable_nop;
>   	intel_encoder->disable = intel_dsi_disable;
>   	intel_encoder->post_disable = intel_dsi_post_disable;
>   	intel_encoder->get_hw_state = intel_dsi_get_hw_state;

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[PATCH] drm/i915: make encoder enable and disable hooks optional

[Jani Nikula]

Encoders are not alike, make enable and disable hooks optional like
other hooks. Utilize this in DSI code, and remove the silly nop hook.

v2: Add the check also to intel_sanitize_encoder() (Madhav)

Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  9 ++++++---
 drivers/gpu/drm/i915/vlv_dsi.c       | 16 ++++------------
 2 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 41abd03ce6a6..de6b4e734292 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5461,7 +5461,8 @@ static void intel_encoders_enable(struct drm_crtc *crtc,
 		if (conn_state->crtc != crtc)
 			continue;
 
-		encoder->enable(encoder, crtc_state, conn_state);
+		if (encoder->enable)
+			encoder->enable(encoder, crtc_state, conn_state);
 		intel_opregion_notify_encoder(encoder, true);
 	}
 }
@@ -5482,7 +5483,8 @@ static void intel_encoders_disable(struct drm_crtc *crtc,
 			continue;
 
 		intel_opregion_notify_encoder(encoder, false);
-		encoder->disable(encoder, old_crtc_state, old_conn_state);
+		if (encoder->disable)
+			encoder->disable(encoder, old_crtc_state, old_conn_state);
 	}
 }
 
@@ -15442,7 +15444,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
 				      encoder->base.base.id,
 				      encoder->base.name);
-			encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
+			if (encoder->disable)
+				encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
 			if (encoder->post_disable)
 				encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
 		}
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index bafeb2a19b90..dbca30460a6b 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -794,6 +794,10 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
  * - wait t4                                           - wait t4
  */
 
+/*
+ * DSI port enable has to be done before pipe and plane enable, so we do it in
+ * the pre_enable hook instead of the enable hook.
+ */
 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *pipe_config,
 				 const struct drm_connector_state *conn_state)
@@ -896,17 +900,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 }
 
 /*
- * DSI port enable has to be done before pipe and plane enable, so we do it in
- * the pre_enable hook.
- */
-static void intel_dsi_enable_nop(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *pipe_config,
-				 const struct drm_connector_state *conn_state)
-{
-	DRM_DEBUG_KMS("\n");
-}
-
-/*
  * DSI port disable has to be done after pipe and plane disable, so we do it in
  * the post_disable hook.
  */
@@ -1764,7 +1757,6 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 
 	intel_encoder->compute_config = intel_dsi_compute_config;
 	intel_encoder->pre_enable = intel_dsi_pre_enable;
-	intel_encoder->enable = intel_dsi_enable_nop;
 	intel_encoder->disable = intel_dsi_disable;
 	intel_encoder->post_disable = intel_dsi_post_disable;
 	intel_encoder->get_hw_state = intel_dsi_get_hw_state;
-- 
2.11.0

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[PATCH v7 02/23] drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()

[Jani Nikula]

Abstract bitrate calculation to a newly resurrected intel_dsi.c file
that will contain common code for VLV and ICL DSI.

No functional changes.

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/Makefile        |  1 +
 drivers/gpu/drm/i915/intel_dsi.c     | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.h     |  3 +++
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 28 ++++++++++------------------
 4 files changed, 31 insertions(+), 18 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 48cae0eae3f9..22cbf9c3bb0c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -143,6 +143,7 @@ i915-y += dvo_ch7017.o \
 	  intel_dp_link_training.o \
 	  intel_dp_mst.o \
 	  intel_dp.o \
+	  intel_dsi.o \
 	  intel_dsi_dcs_backlight.o \
 	  intel_dsi_vbt.o \
 	  intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
new file mode 100644
index 000000000000..4daa1da94047
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include <drm/drm_mipi_dsi.h>
+#include "intel_dsi.h"
+
+int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
+{
+	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+
+	if (WARN_ON(bpp < 0))
+		bpp = 16;
+
+	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index ad7c1cb32983..68f14d8f1e18 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -129,6 +129,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 	return container_of(encoder, struct intel_dsi, base.base);
 }
 
+/* intel_dsi.c */
+int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
+
 /* vlv_dsi.c */
 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index ac83d6b89ae0..6c4cc92f5947 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -506,14 +506,12 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
-	u32 bpp;
-	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
+	u32 tlpx_ns, extra_byte_count, tlpx_ui;
 	u32 ui_num, ui_den;
 	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
 	u32 ths_prepare_ns, tclk_trail_ns;
 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
 	u32 lp_to_hs_switch, hs_to_lp_switch;
-	u32 pclk, computed_ddr;
 	u32 mul;
 	u16 burst_mode_ratio;
 	enum port port;
@@ -526,7 +524,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->pixel_format =
 			pixel_format_from_register_bits(
 				mipi_config->videomode_color_format << 7);
-	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 	intel_dsi->dual_link = mipi_config->dual_link;
 	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
@@ -541,19 +538,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->video_frmt_cfg_bits =
 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 
-	pclk = mode->clock;
+	/* Starting point, adjusted depending on dual link and burst mode */
+	intel_dsi->pclk = mode->clock;
 
 	/* In dual link mode each port needs half of pixel clock */
 	if (intel_dsi->dual_link) {
-		pclk = pclk / 2;
+		intel_dsi->pclk /= 2;
 
 		/* we can enable pixel_overlap if needed by panel. In this
 		 * case we need to increase the pixelclock for extra pixels
 		 */
 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
-			pclk += DIV_ROUND_UP(mode->vtotal *
-						intel_dsi->pixel_overlap *
-						60, 1000);
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
 		}
 	}
 
@@ -563,19 +559,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	 */
 	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 		if (mipi_config->target_burst_mode_freq) {
-			computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
+			u32 bitrate = intel_dsi_bitrate(intel_dsi);
 
-			if (mipi_config->target_burst_mode_freq <
-								computed_ddr) {
+			if (mipi_config->target_burst_mode_freq < bitrate) {
 				DRM_ERROR("Burst mode freq is less than computed\n");
 				return false;
 			}
 
 			burst_mode_ratio = DIV_ROUND_UP(
 				mipi_config->target_burst_mode_freq * 100,
-				computed_ddr);
+				bitrate);
 
-			pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
+			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
 		} else {
 			DRM_ERROR("Burst mode target is not set\n");
 			return false;
@@ -584,9 +579,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 		burst_mode_ratio = 100;
 
 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
-	intel_dsi->pclk = pclk;
-
-	bitrate = (pclk * bpp) / intel_dsi->lane_count;
 
 	switch (intel_dsi->escape_clk_div) {
 	case 0:
@@ -620,7 +612,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	/* in Kbps */
 	ui_num = NS_KHZ_RATIO;
-	ui_den = bitrate;
+	ui_den = intel_dsi_bitrate(intel_dsi);
 
 	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
-- 
2.11.0

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Re: [PATCH v7 02/23] drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> Abstract bitrate calculation to a newly resurrected intel_dsi.c file
> that will contain common code for VLV and ICL DSI.
>
> No functional changes.
>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile        |  1 +
>   drivers/gpu/drm/i915/intel_dsi.c     | 17 +++++++++++++++++
>   drivers/gpu/drm/i915/intel_dsi.h     |  3 +++
>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 28 ++++++++++------------------
>   4 files changed, 31 insertions(+), 18 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 48cae0eae3f9..22cbf9c3bb0c 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -143,6 +143,7 @@ i915-y += dvo_ch7017.o \
>   	  intel_dp_link_training.o \
>   	  intel_dp_mst.o \
>   	  intel_dp.o \
> +	  intel_dsi.o \
>   	  intel_dsi_dcs_backlight.o \
>   	  intel_dsi_vbt.o \
>   	  intel_dvo.o \
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> new file mode 100644
> index 000000000000..4daa1da94047
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2018 Intel Corporation
> + */
> +
> +#include <drm/drm_mipi_dsi.h>
> +#include "intel_dsi.h"
> +
> +int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
> +{
> +	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> +
> +	if (WARN_ON(bpp < 0))
> +		bpp = 16;

Shouldn't we keep the default bpp to 24 here as in most of the cases bpp 
is 24 for DSI or why 16??

Regards,
Madhav

> +
> +	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index ad7c1cb32983..68f14d8f1e18 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -129,6 +129,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>   	return container_of(encoder, struct intel_dsi, base.base);
>   }
>   
> +/* intel_dsi.c */
> +int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
> +
>   /* vlv_dsi.c */
>   void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>   enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index ac83d6b89ae0..6c4cc92f5947 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -506,14 +506,12 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>   	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
>   	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
> -	u32 bpp;
> -	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
> +	u32 tlpx_ns, extra_byte_count, tlpx_ui;
>   	u32 ui_num, ui_den;
>   	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>   	u32 ths_prepare_ns, tclk_trail_ns;
>   	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>   	u32 lp_to_hs_switch, hs_to_lp_switch;
> -	u32 pclk, computed_ddr;
>   	u32 mul;
>   	u16 burst_mode_ratio;
>   	enum port port;
> @@ -526,7 +524,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   	intel_dsi->pixel_format =
>   			pixel_format_from_register_bits(
>   				mipi_config->videomode_color_format << 7);
> -	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>   
>   	intel_dsi->dual_link = mipi_config->dual_link;
>   	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
> @@ -541,19 +538,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   	intel_dsi->video_frmt_cfg_bits =
>   		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
>   
> -	pclk = mode->clock;
> +	/* Starting point, adjusted depending on dual link and burst mode */
> +	intel_dsi->pclk = mode->clock;
>   
>   	/* In dual link mode each port needs half of pixel clock */
>   	if (intel_dsi->dual_link) {
> -		pclk = pclk / 2;
> +		intel_dsi->pclk /= 2;
>   
>   		/* we can enable pixel_overlap if needed by panel. In this
>   		 * case we need to increase the pixelclock for extra pixels
>   		 */
>   		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> -			pclk += DIV_ROUND_UP(mode->vtotal *
> -						intel_dsi->pixel_overlap *
> -						60, 1000);
> +			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
>   		}
>   	}
>   
> @@ -563,19 +559,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   	 */
>   	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
>   		if (mipi_config->target_burst_mode_freq) {
> -			computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
> +			u32 bitrate = intel_dsi_bitrate(intel_dsi);
>   
> -			if (mipi_config->target_burst_mode_freq <
> -								computed_ddr) {
> +			if (mipi_config->target_burst_mode_freq < bitrate) {
>   				DRM_ERROR("Burst mode freq is less than computed\n");
>   				return false;
>   			}
>   
>   			burst_mode_ratio = DIV_ROUND_UP(
>   				mipi_config->target_burst_mode_freq * 100,
> -				computed_ddr);
> +				bitrate);
>   
> -			pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
> +			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
>   		} else {
>   			DRM_ERROR("Burst mode target is not set\n");
>   			return false;
> @@ -584,9 +579,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   		burst_mode_ratio = 100;
>   
>   	intel_dsi->burst_mode_ratio = burst_mode_ratio;
> -	intel_dsi->pclk = pclk;
> -
> -	bitrate = (pclk * bpp) / intel_dsi->lane_count;
>   
>   	switch (intel_dsi->escape_clk_div) {
>   	case 0:
> @@ -620,7 +612,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   
>   	/* in Kbps */
>   	ui_num = NS_KHZ_RATIO;
> -	ui_den = bitrate;
> +	ui_den = intel_dsi_bitrate(intel_dsi);
>   
>   	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
>   	ths_prepare_hszero = mipi_config->ths_prepare_hszero;

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Re: [PATCH v7 02/23] drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()

[Jani Nikula]

On Tue, 16 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>> Abstract bitrate calculation to a newly resurrected intel_dsi.c file
>> that will contain common code for VLV and ICL DSI.
>>
>> No functional changes.
>>
>> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>   drivers/gpu/drm/i915/Makefile        |  1 +
>>   drivers/gpu/drm/i915/intel_dsi.c     | 17 +++++++++++++++++
>>   drivers/gpu/drm/i915/intel_dsi.h     |  3 +++
>>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 28 ++++++++++------------------
>>   4 files changed, 31 insertions(+), 18 deletions(-)
>>   create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 48cae0eae3f9..22cbf9c3bb0c 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -143,6 +143,7 @@ i915-y += dvo_ch7017.o \
>>   	  intel_dp_link_training.o \
>>   	  intel_dp_mst.o \
>>   	  intel_dp.o \
>> +	  intel_dsi.o \
>>   	  intel_dsi_dcs_backlight.o \
>>   	  intel_dsi_vbt.o \
>>   	  intel_dvo.o \
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> new file mode 100644
>> index 000000000000..4daa1da94047
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -0,0 +1,17 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2018 Intel Corporation
>> + */
>> +
>> +#include <drm/drm_mipi_dsi.h>
>> +#include "intel_dsi.h"
>> +
>> +int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
>> +{
>> +	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>> +
>> +	if (WARN_ON(bpp < 0))
>> +		bpp = 16;
>
> Shouldn't we keep the default bpp to 24 here as in most of the cases bpp 
> is 24 for DSI or why 16??

*shrug*

Not sure it matters all that much really. We set the pixel format in
intel_dsi_vbt.c, and if that gives us something bogus, not much of a
chance any of it will work. More than anything I just wanted to avoid a
negative return from this function.

BR,
Jani.

>
> Regards,
> Madhav
>
>> +
>> +	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index ad7c1cb32983..68f14d8f1e18 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -129,6 +129,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>>   	return container_of(encoder, struct intel_dsi, base.base);
>>   }
>>   
>> +/* intel_dsi.c */
>> +int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
>> +
>>   /* vlv_dsi.c */
>>   void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>>   enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index ac83d6b89ae0..6c4cc92f5947 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -506,14 +506,12 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>>   	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
>>   	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
>> -	u32 bpp;
>> -	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
>> +	u32 tlpx_ns, extra_byte_count, tlpx_ui;
>>   	u32 ui_num, ui_den;
>>   	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>>   	u32 ths_prepare_ns, tclk_trail_ns;
>>   	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>>   	u32 lp_to_hs_switch, hs_to_lp_switch;
>> -	u32 pclk, computed_ddr;
>>   	u32 mul;
>>   	u16 burst_mode_ratio;
>>   	enum port port;
>> @@ -526,7 +524,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   	intel_dsi->pixel_format =
>>   			pixel_format_from_register_bits(
>>   				mipi_config->videomode_color_format << 7);
>> -	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>>   
>>   	intel_dsi->dual_link = mipi_config->dual_link;
>>   	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>> @@ -541,19 +538,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   	intel_dsi->video_frmt_cfg_bits =
>>   		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
>>   
>> -	pclk = mode->clock;
>> +	/* Starting point, adjusted depending on dual link and burst mode */
>> +	intel_dsi->pclk = mode->clock;
>>   
>>   	/* In dual link mode each port needs half of pixel clock */
>>   	if (intel_dsi->dual_link) {
>> -		pclk = pclk / 2;
>> +		intel_dsi->pclk /= 2;
>>   
>>   		/* we can enable pixel_overlap if needed by panel. In this
>>   		 * case we need to increase the pixelclock for extra pixels
>>   		 */
>>   		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> -			pclk += DIV_ROUND_UP(mode->vtotal *
>> -						intel_dsi->pixel_overlap *
>> -						60, 1000);
>> +			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
>>   		}
>>   	}
>>   
>> @@ -563,19 +559,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   	 */
>>   	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
>>   		if (mipi_config->target_burst_mode_freq) {
>> -			computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
>> +			u32 bitrate = intel_dsi_bitrate(intel_dsi);
>>   
>> -			if (mipi_config->target_burst_mode_freq <
>> -								computed_ddr) {
>> +			if (mipi_config->target_burst_mode_freq < bitrate) {
>>   				DRM_ERROR("Burst mode freq is less than computed\n");
>>   				return false;
>>   			}
>>   
>>   			burst_mode_ratio = DIV_ROUND_UP(
>>   				mipi_config->target_burst_mode_freq * 100,
>> -				computed_ddr);
>> +				bitrate);
>>   
>> -			pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
>> +			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
>>   		} else {
>>   			DRM_ERROR("Burst mode target is not set\n");
>>   			return false;
>> @@ -584,9 +579,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   		burst_mode_ratio = 100;
>>   
>>   	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>> -	intel_dsi->pclk = pclk;
>> -
>> -	bitrate = (pclk * bpp) / intel_dsi->lane_count;
>>   
>>   	switch (intel_dsi->escape_clk_div) {
>>   	case 0:
>> @@ -620,7 +612,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   
>>   	/* in Kbps */
>>   	ui_num = NS_KHZ_RATIO;
>> -	ui_den = bitrate;
>> +	ui_den = intel_dsi_bitrate(intel_dsi);
>>   
>>   	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
>>   	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v7 02/23] drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()

[Madhav Chauhan]

On 10/16/2018 6:14 PM, Jani Nikula wrote:
> On Tue, 16 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>>> Abstract bitrate calculation to a newly resurrected intel_dsi.c file
>>> that will contain common code for VLV and ICL DSI.
>>>
>>> No functional changes.
>>>
>>> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
>>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/Makefile        |  1 +
>>>    drivers/gpu/drm/i915/intel_dsi.c     | 17 +++++++++++++++++
>>>    drivers/gpu/drm/i915/intel_dsi.h     |  3 +++
>>>    drivers/gpu/drm/i915/intel_dsi_vbt.c | 28 ++++++++++------------------
>>>    4 files changed, 31 insertions(+), 18 deletions(-)
>>>    create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
>>>
>>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>>> index 48cae0eae3f9..22cbf9c3bb0c 100644
>>> --- a/drivers/gpu/drm/i915/Makefile
>>> +++ b/drivers/gpu/drm/i915/Makefile
>>> @@ -143,6 +143,7 @@ i915-y += dvo_ch7017.o \
>>>    	  intel_dp_link_training.o \
>>>    	  intel_dp_mst.o \
>>>    	  intel_dp.o \
>>> +	  intel_dsi.o \
>>>    	  intel_dsi_dcs_backlight.o \
>>>    	  intel_dsi_vbt.o \
>>>    	  intel_dvo.o \
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>> new file mode 100644
>>> index 000000000000..4daa1da94047
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>> @@ -0,0 +1,17 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2018 Intel Corporation
>>> + */
>>> +
>>> +#include <drm/drm_mipi_dsi.h>
>>> +#include "intel_dsi.h"
>>> +
>>> +int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
>>> +{
>>> +	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>>> +
>>> +	if (WARN_ON(bpp < 0))
>>> +		bpp = 16;
>> Shouldn't we keep the default bpp to 24 here as in most of the cases bpp
>> is 24 for DSI or why 16??
> *shrug*
>
> Not sure it matters all that much really. We set the pixel format in
> intel_dsi_vbt.c, and if that gives us something bogus, not much of a
> chance any of it will work. More than anything I just wanted to avoid a
> negative return from this function.

Agree,
Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>

Regards,
Madhav

>
> BR,
> Jani.
>
>> Regards,
>> Madhav
>>
>>> +
>>> +	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>> index ad7c1cb32983..68f14d8f1e18 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>> @@ -129,6 +129,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>>>    	return container_of(encoder, struct intel_dsi, base.base);
>>>    }
>>>    
>>> +/* intel_dsi.c */
>>> +int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
>>> +
>>>    /* vlv_dsi.c */
>>>    void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>>>    enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> index ac83d6b89ae0..6c4cc92f5947 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> @@ -506,14 +506,12 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>>    	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>>>    	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
>>>    	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
>>> -	u32 bpp;
>>> -	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
>>> +	u32 tlpx_ns, extra_byte_count, tlpx_ui;
>>>    	u32 ui_num, ui_den;
>>>    	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>>>    	u32 ths_prepare_ns, tclk_trail_ns;
>>>    	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>>>    	u32 lp_to_hs_switch, hs_to_lp_switch;
>>> -	u32 pclk, computed_ddr;
>>>    	u32 mul;
>>>    	u16 burst_mode_ratio;
>>>    	enum port port;
>>> @@ -526,7 +524,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>>    	intel_dsi->pixel_format =
>>>    			pixel_format_from_register_bits(
>>>    				mipi_config->videomode_color_format << 7);
>>> -	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>>>    
>>>    	intel_dsi->dual_link = mipi_config->dual_link;
>>>    	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>>> @@ -541,19 +538,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>>    	intel_dsi->video_frmt_cfg_bits =
>>>    		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
>>>    
>>> -	pclk = mode->clock;
>>> +	/* Starting point, adjusted depending on dual link and burst mode */
>>> +	intel_dsi->pclk = mode->clock;
>>>    
>>>    	/* In dual link mode each port needs half of pixel clock */
>>>    	if (intel_dsi->dual_link) {
>>> -		pclk = pclk / 2;
>>> +		intel_dsi->pclk /= 2;
>>>    
>>>    		/* we can enable pixel_overlap if needed by panel. In this
>>>    		 * case we need to increase the pixelclock for extra pixels
>>>    		 */
>>>    		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>> -			pclk += DIV_ROUND_UP(mode->vtotal *
>>> -						intel_dsi->pixel_overlap *
>>> -						60, 1000);
>>> +			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
>>>    		}
>>>    	}
>>>    
>>> @@ -563,19 +559,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>>    	 */
>>>    	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
>>>    		if (mipi_config->target_burst_mode_freq) {
>>> -			computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
>>> +			u32 bitrate = intel_dsi_bitrate(intel_dsi);
>>>    
>>> -			if (mipi_config->target_burst_mode_freq <
>>> -								computed_ddr) {
>>> +			if (mipi_config->target_burst_mode_freq < bitrate) {
>>>    				DRM_ERROR("Burst mode freq is less than computed\n");
>>>    				return false;
>>>    			}
>>>    
>>>    			burst_mode_ratio = DIV_ROUND_UP(
>>>    				mipi_config->target_burst_mode_freq * 100,
>>> -				computed_ddr);
>>> +				bitrate);
>>>    
>>> -			pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
>>> +			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
>>>    		} else {
>>>    			DRM_ERROR("Burst mode target is not set\n");
>>>    			return false;
>>> @@ -584,9 +579,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>>    		burst_mode_ratio = 100;
>>>    
>>>    	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>>> -	intel_dsi->pclk = pclk;
>>> -
>>> -	bitrate = (pclk * bpp) / intel_dsi->lane_count;
>>>    
>>>    	switch (intel_dsi->escape_clk_div) {
>>>    	case 0:
>>> @@ -620,7 +612,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>>    
>>>    	/* in Kbps */
>>>    	ui_num = NS_KHZ_RATIO;
>>> -	ui_den = bitrate;
>>> +	ui_den = intel_dsi_bitrate(intel_dsi);
>>>    
>>>    	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
>>>    	ths_prepare_hszero = mipi_config->ths_prepare_hszero;

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[PATCH v7 03/23] drm/i915/dsi: abstract dphy parameter init

[Jani Nikula]

intel_dsi_vbt_init() has grown too unwieldy, and it's about to be
modified due to ICL DSI. Abstract out the VLV specific dphy param
init. No functional changes. Intentionally no stylistic changes during
code movement.

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 147 +++++++++++++++++++----------------
 1 file changed, 78 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 6c4cc92f5947..fdeba8386d53 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -499,13 +499,11 @@ int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
 	return 1;
 }
 
-bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
+static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
-	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
-	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 	u32 tlpx_ns, extra_byte_count, tlpx_ui;
 	u32 ui_num, ui_den;
 	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
@@ -513,72 +511,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
 	u32 lp_to_hs_switch, hs_to_lp_switch;
 	u32 mul;
-	u16 burst_mode_ratio;
-	enum port port;
-
-	DRM_DEBUG_KMS("\n");
-
-	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
-	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
-	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
-	intel_dsi->pixel_format =
-			pixel_format_from_register_bits(
-				mipi_config->videomode_color_format << 7);
-
-	intel_dsi->dual_link = mipi_config->dual_link;
-	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
-	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
-	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
-	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
-	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
-	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
-	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
-	intel_dsi->init_count = mipi_config->master_init_timer;
-	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
-	intel_dsi->video_frmt_cfg_bits =
-		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
-
-	/* Starting point, adjusted depending on dual link and burst mode */
-	intel_dsi->pclk = mode->clock;
-
-	/* In dual link mode each port needs half of pixel clock */
-	if (intel_dsi->dual_link) {
-		intel_dsi->pclk /= 2;
-
-		/* we can enable pixel_overlap if needed by panel. In this
-		 * case we need to increase the pixelclock for extra pixels
-		 */
-		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
-			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
-		}
-	}
-
-	/* Burst Mode Ratio
-	 * Target ddr frequency from VBT / non burst ddr freq
-	 * multiply by 100 to preserve remainder
-	 */
-	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
-		if (mipi_config->target_burst_mode_freq) {
-			u32 bitrate = intel_dsi_bitrate(intel_dsi);
-
-			if (mipi_config->target_burst_mode_freq < bitrate) {
-				DRM_ERROR("Burst mode freq is less than computed\n");
-				return false;
-			}
-
-			burst_mode_ratio = DIV_ROUND_UP(
-				mipi_config->target_burst_mode_freq * 100,
-				bitrate);
-
-			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
-		} else {
-			DRM_ERROR("Burst mode target is not set\n");
-			return false;
-		}
-	} else
-		burst_mode_ratio = 100;
-
-	intel_dsi->burst_mode_ratio = burst_mode_ratio;
 
 	switch (intel_dsi->escape_clk_div) {
 	case 0:
@@ -738,6 +670,83 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
 			8);
 	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
+}
+
+bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
+	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
+	u16 burst_mode_ratio;
+	enum port port;
+
+	DRM_DEBUG_KMS("\n");
+
+	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
+	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
+	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
+	intel_dsi->pixel_format =
+			pixel_format_from_register_bits(
+				mipi_config->videomode_color_format << 7);
+
+	intel_dsi->dual_link = mipi_config->dual_link;
+	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
+	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
+	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
+	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
+	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
+	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
+	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
+	intel_dsi->init_count = mipi_config->master_init_timer;
+	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
+	intel_dsi->video_frmt_cfg_bits =
+		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
+
+	/* Starting point, adjusted depending on dual link and burst mode */
+	intel_dsi->pclk = mode->clock;
+
+	/* In dual link mode each port needs half of pixel clock */
+	if (intel_dsi->dual_link) {
+		intel_dsi->pclk /= 2;
+
+		/* we can enable pixel_overlap if needed by panel. In this
+		 * case we need to increase the pixelclock for extra pixels
+		 */
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
+		}
+	}
+
+	/* Burst Mode Ratio
+	 * Target ddr frequency from VBT / non burst ddr freq
+	 * multiply by 100 to preserve remainder
+	 */
+	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
+		if (mipi_config->target_burst_mode_freq) {
+			u32 bitrate = intel_dsi_bitrate(intel_dsi);
+
+			if (mipi_config->target_burst_mode_freq < bitrate) {
+				DRM_ERROR("Burst mode freq is less than computed\n");
+				return false;
+			}
+
+			burst_mode_ratio = DIV_ROUND_UP(
+				mipi_config->target_burst_mode_freq * 100,
+				bitrate);
+
+			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
+		} else {
+			DRM_ERROR("Burst mode target is not set\n");
+			return false;
+		}
+	} else
+		burst_mode_ratio = 100;
+
+	intel_dsi->burst_mode_ratio = burst_mode_ratio;
+
+	vlv_dphy_param_init(intel_dsi);
 
 	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
 	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
-- 
2.11.0

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Re: [PATCH v7 03/23] drm/i915/dsi: abstract dphy parameter init

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> intel_dsi_vbt_init() has grown too unwieldy, and it's about to be
> modified due to ICL DSI. Abstract out the VLV specific dphy param
> init. No functional changes. Intentionally no stylistic changes during
> code movement.
>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Looks ok to me,
Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>

Regards,
Madhav

> ---
>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 147 +++++++++++++++++++----------------
>   1 file changed, 78 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 6c4cc92f5947..fdeba8386d53 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -499,13 +499,11 @@ int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
>   	return 1;
>   }
>   
> -bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
> +static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>   {
>   	struct drm_device *dev = intel_dsi->base.base.dev;
>   	struct drm_i915_private *dev_priv = to_i915(dev);
>   	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> -	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
> -	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
>   	u32 tlpx_ns, extra_byte_count, tlpx_ui;
>   	u32 ui_num, ui_den;
>   	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> @@ -513,72 +511,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>   	u32 lp_to_hs_switch, hs_to_lp_switch;
>   	u32 mul;
> -	u16 burst_mode_ratio;
> -	enum port port;
> -
> -	DRM_DEBUG_KMS("\n");
> -
> -	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
> -	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
> -	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
> -	intel_dsi->pixel_format =
> -			pixel_format_from_register_bits(
> -				mipi_config->videomode_color_format << 7);
> -
> -	intel_dsi->dual_link = mipi_config->dual_link;
> -	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
> -	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
> -	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
> -	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
> -	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
> -	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
> -	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
> -	intel_dsi->init_count = mipi_config->master_init_timer;
> -	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
> -	intel_dsi->video_frmt_cfg_bits =
> -		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
> -
> -	/* Starting point, adjusted depending on dual link and burst mode */
> -	intel_dsi->pclk = mode->clock;
> -
> -	/* In dual link mode each port needs half of pixel clock */
> -	if (intel_dsi->dual_link) {
> -		intel_dsi->pclk /= 2;
> -
> -		/* we can enable pixel_overlap if needed by panel. In this
> -		 * case we need to increase the pixelclock for extra pixels
> -		 */
> -		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> -			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
> -		}
> -	}
> -
> -	/* Burst Mode Ratio
> -	 * Target ddr frequency from VBT / non burst ddr freq
> -	 * multiply by 100 to preserve remainder
> -	 */
> -	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
> -		if (mipi_config->target_burst_mode_freq) {
> -			u32 bitrate = intel_dsi_bitrate(intel_dsi);
> -
> -			if (mipi_config->target_burst_mode_freq < bitrate) {
> -				DRM_ERROR("Burst mode freq is less than computed\n");
> -				return false;
> -			}
> -
> -			burst_mode_ratio = DIV_ROUND_UP(
> -				mipi_config->target_burst_mode_freq * 100,
> -				bitrate);
> -
> -			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
> -		} else {
> -			DRM_ERROR("Burst mode target is not set\n");
> -			return false;
> -		}
> -	} else
> -		burst_mode_ratio = 100;
> -
> -	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>   
>   	switch (intel_dsi->escape_clk_div) {
>   	case 0:
> @@ -738,6 +670,83 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
>   			8);
>   	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
> +}
> +
> +bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
> +{
> +	struct drm_device *dev = intel_dsi->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> +	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
> +	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
> +	u16 burst_mode_ratio;
> +	enum port port;
> +
> +	DRM_DEBUG_KMS("\n");
> +
> +	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
> +	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
> +	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
> +	intel_dsi->pixel_format =
> +			pixel_format_from_register_bits(
> +				mipi_config->videomode_color_format << 7);
> +
> +	intel_dsi->dual_link = mipi_config->dual_link;
> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
> +	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
> +	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
> +	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
> +	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
> +	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
> +	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
> +	intel_dsi->init_count = mipi_config->master_init_timer;
> +	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
> +	intel_dsi->video_frmt_cfg_bits =
> +		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
> +
> +	/* Starting point, adjusted depending on dual link and burst mode */
> +	intel_dsi->pclk = mode->clock;
> +
> +	/* In dual link mode each port needs half of pixel clock */
> +	if (intel_dsi->dual_link) {
> +		intel_dsi->pclk /= 2;
> +
> +		/* we can enable pixel_overlap if needed by panel. In this
> +		 * case we need to increase the pixelclock for extra pixels
> +		 */
> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> +			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
> +		}
> +	}
> +
> +	/* Burst Mode Ratio
> +	 * Target ddr frequency from VBT / non burst ddr freq
> +	 * multiply by 100 to preserve remainder
> +	 */
> +	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
> +		if (mipi_config->target_burst_mode_freq) {
> +			u32 bitrate = intel_dsi_bitrate(intel_dsi);
> +
> +			if (mipi_config->target_burst_mode_freq < bitrate) {
> +				DRM_ERROR("Burst mode freq is less than computed\n");
> +				return false;
> +			}
> +
> +			burst_mode_ratio = DIV_ROUND_UP(
> +				mipi_config->target_burst_mode_freq * 100,
> +				bitrate);
> +
> +			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
> +		} else {
> +			DRM_ERROR("Burst mode target is not set\n");
> +			return false;
> +		}
> +	} else
> +		burst_mode_ratio = 100;
> +
> +	intel_dsi->burst_mode_ratio = burst_mode_ratio;
> +
> +	vlv_dphy_param_init(intel_dsi);
>   
>   	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
>   	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);

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Re: [PATCH v7 03/23] drm/i915/dsi: abstract dphy parameter init

[Jani Nikula]

On Tue, 16 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>> intel_dsi_vbt_init() has grown too unwieldy, and it's about to be
>> modified due to ICL DSI. Abstract out the VLV specific dphy param
>> init. No functional changes. Intentionally no stylistic changes during
>> code movement.
>>
>> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Looks ok to me,
> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>

Thanks for the review, pushed patches 1-3 with Ville's IRC ack on patch
1.

BR,
Jani.


>
> Regards,
> Madhav
>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 147 +++++++++++++++++++----------------
>>   1 file changed, 78 insertions(+), 69 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index 6c4cc92f5947..fdeba8386d53 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -499,13 +499,11 @@ int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
>>   	return 1;
>>   }
>>   
>> -bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>> +static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>>   {
>>   	struct drm_device *dev = intel_dsi->base.base.dev;
>>   	struct drm_i915_private *dev_priv = to_i915(dev);
>>   	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>> -	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
>> -	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
>>   	u32 tlpx_ns, extra_byte_count, tlpx_ui;
>>   	u32 ui_num, ui_den;
>>   	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>> @@ -513,72 +511,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>>   	u32 lp_to_hs_switch, hs_to_lp_switch;
>>   	u32 mul;
>> -	u16 burst_mode_ratio;
>> -	enum port port;
>> -
>> -	DRM_DEBUG_KMS("\n");
>> -
>> -	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
>> -	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>> -	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>> -	intel_dsi->pixel_format =
>> -			pixel_format_from_register_bits(
>> -				mipi_config->videomode_color_format << 7);
>> -
>> -	intel_dsi->dual_link = mipi_config->dual_link;
>> -	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>> -	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
>> -	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
>> -	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
>> -	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
>> -	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
>> -	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
>> -	intel_dsi->init_count = mipi_config->master_init_timer;
>> -	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
>> -	intel_dsi->video_frmt_cfg_bits =
>> -		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
>> -
>> -	/* Starting point, adjusted depending on dual link and burst mode */
>> -	intel_dsi->pclk = mode->clock;
>> -
>> -	/* In dual link mode each port needs half of pixel clock */
>> -	if (intel_dsi->dual_link) {
>> -		intel_dsi->pclk /= 2;
>> -
>> -		/* we can enable pixel_overlap if needed by panel. In this
>> -		 * case we need to increase the pixelclock for extra pixels
>> -		 */
>> -		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> -			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
>> -		}
>> -	}
>> -
>> -	/* Burst Mode Ratio
>> -	 * Target ddr frequency from VBT / non burst ddr freq
>> -	 * multiply by 100 to preserve remainder
>> -	 */
>> -	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
>> -		if (mipi_config->target_burst_mode_freq) {
>> -			u32 bitrate = intel_dsi_bitrate(intel_dsi);
>> -
>> -			if (mipi_config->target_burst_mode_freq < bitrate) {
>> -				DRM_ERROR("Burst mode freq is less than computed\n");
>> -				return false;
>> -			}
>> -
>> -			burst_mode_ratio = DIV_ROUND_UP(
>> -				mipi_config->target_burst_mode_freq * 100,
>> -				bitrate);
>> -
>> -			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
>> -		} else {
>> -			DRM_ERROR("Burst mode target is not set\n");
>> -			return false;
>> -		}
>> -	} else
>> -		burst_mode_ratio = 100;
>> -
>> -	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>>   
>>   	switch (intel_dsi->escape_clk_div) {
>>   	case 0:
>> @@ -738,6 +670,83 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
>>   			8);
>>   	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
>> +}
>> +
>> +bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>> +{
>> +	struct drm_device *dev = intel_dsi->base.base.dev;
>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>> +	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
>> +	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
>> +	u16 burst_mode_ratio;
>> +	enum port port;
>> +
>> +	DRM_DEBUG_KMS("\n");
>> +
>> +	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
>> +	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>> +	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>> +	intel_dsi->pixel_format =
>> +			pixel_format_from_register_bits(
>> +				mipi_config->videomode_color_format << 7);
>> +
>> +	intel_dsi->dual_link = mipi_config->dual_link;
>> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>> +	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
>> +	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
>> +	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
>> +	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
>> +	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
>> +	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
>> +	intel_dsi->init_count = mipi_config->master_init_timer;
>> +	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
>> +	intel_dsi->video_frmt_cfg_bits =
>> +		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
>> +
>> +	/* Starting point, adjusted depending on dual link and burst mode */
>> +	intel_dsi->pclk = mode->clock;
>> +
>> +	/* In dual link mode each port needs half of pixel clock */
>> +	if (intel_dsi->dual_link) {
>> +		intel_dsi->pclk /= 2;
>> +
>> +		/* we can enable pixel_overlap if needed by panel. In this
>> +		 * case we need to increase the pixelclock for extra pixels
>> +		 */
>> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> +			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
>> +		}
>> +	}
>> +
>> +	/* Burst Mode Ratio
>> +	 * Target ddr frequency from VBT / non burst ddr freq
>> +	 * multiply by 100 to preserve remainder
>> +	 */
>> +	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
>> +		if (mipi_config->target_burst_mode_freq) {
>> +			u32 bitrate = intel_dsi_bitrate(intel_dsi);
>> +
>> +			if (mipi_config->target_burst_mode_freq < bitrate) {
>> +				DRM_ERROR("Burst mode freq is less than computed\n");
>> +				return false;
>> +			}
>> +
>> +			burst_mode_ratio = DIV_ROUND_UP(
>> +				mipi_config->target_burst_mode_freq * 100,
>> +				bitrate);
>> +
>> +			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
>> +		} else {
>> +			DRM_ERROR("Burst mode target is not set\n");
>> +			return false;
>> +		}
>> +	} else
>> +		burst_mode_ratio = 100;
>> +
>> +	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>> +
>> +	vlv_dphy_param_init(intel_dsi);
>>   
>>   	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
>>   	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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[PATCH v7 04/23] drm/i915/dsi: abstract intel_dsi_tlpx_ns()

[Jani Nikula]

Will be needed in the future. No functional changes.

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c     | 13 +++++++++++++
 drivers/gpu/drm/i915/intel_dsi.h     |  1 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 16 +---------------
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4daa1da94047..a32cc1f4b384 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -15,3 +15,16 @@ int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
 
 	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
 }
+
+int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
+{
+	switch (intel_dsi->escape_clk_div) {
+	default:
+	case 0:
+		return 50;
+	case 1:
+		return 100;
+	case 2:
+		return 200;
+	}
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 68f14d8f1e18..0d911a4adfaa 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -131,6 +131,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 
 /* intel_dsi.c */
 int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
+int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
 
 /* vlv_dsi.c */
 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index fdeba8386d53..b0d8548f0462 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -512,21 +512,7 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
 	u32 lp_to_hs_switch, hs_to_lp_switch;
 	u32 mul;
 
-	switch (intel_dsi->escape_clk_div) {
-	case 0:
-		tlpx_ns = 50;
-		break;
-	case 1:
-		tlpx_ns = 100;
-		break;
-
-	case 2:
-		tlpx_ns = 200;
-		break;
-	default:
-		tlpx_ns = 50;
-		break;
-	}
+	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
 
 	switch (intel_dsi->lane_count) {
 	case 1:
-- 
2.11.0

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Re: [PATCH v7 04/23] drm/i915/dsi: abstract intel_dsi_tlpx_ns()

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> Will be needed in the future. No functional changes.

Agree, will be needing this while setting up DSI protocol timeouts for ICL.

>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dsi.c     | 13 +++++++++++++
>   drivers/gpu/drm/i915/intel_dsi.h     |  1 +
>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 16 +---------------
>   3 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 4daa1da94047..a32cc1f4b384 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -15,3 +15,16 @@ int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
>   
>   	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
>   }
> +
> +int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
> +{
> +	switch (intel_dsi->escape_clk_div) {
> +	default:
> +	case 0:
> +		return 50;
> +	case 1:
> +		return 100;
> +	case 2:
> +		return 200;
> +	}
> +}

Can we change the return of this function to unsigned int, there is no way
that this function can return < 0  as per current implementation??

Regards,
Madhav

> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 68f14d8f1e18..0d911a4adfaa 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -131,6 +131,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>   
>   /* intel_dsi.c */
>   int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
> +int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
>   
>   /* vlv_dsi.c */
>   void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index fdeba8386d53..b0d8548f0462 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -512,21 +512,7 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>   	u32 lp_to_hs_switch, hs_to_lp_switch;
>   	u32 mul;
>   
> -	switch (intel_dsi->escape_clk_div) {
> -	case 0:
> -		tlpx_ns = 50;
> -		break;
> -	case 1:
> -		tlpx_ns = 100;
> -		break;
> -
> -	case 2:
> -		tlpx_ns = 200;
> -		break;
> -	default:
> -		tlpx_ns = 50;
> -		break;
> -	}
> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
>   
>   	switch (intel_dsi->lane_count) {
>   	case 1:

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Re: [PATCH v7 04/23] drm/i915/dsi: abstract intel_dsi_tlpx_ns()

[Jani Nikula]

On Tue, 16 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>> Will be needed in the future. No functional changes.
>
> Agree, will be needing this while setting up DSI protocol timeouts for ICL.
>
>>
>> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi.c     | 13 +++++++++++++
>>   drivers/gpu/drm/i915/intel_dsi.h     |  1 +
>>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 16 +---------------
>>   3 files changed, 15 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 4daa1da94047..a32cc1f4b384 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -15,3 +15,16 @@ int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
>>   
>>   	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
>>   }
>> +
>> +int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
>> +{
>> +	switch (intel_dsi->escape_clk_div) {
>> +	default:
>> +	case 0:
>> +		return 50;
>> +	case 1:
>> +		return 100;
>> +	case 2:
>> +		return 200;
>> +	}
>> +}
>
> Can we change the return of this function to unsigned int, there is no way
> that this function can return < 0  as per current implementation??

I'd rather not. I'm sure I should be able to justify this exhaustively
with examples, but I think gratuitous use of unsigned types leads to
issues with integer promotions and signed/unsigned comparisons etc. So
if it's "just a number", used for arithmetics, I'll pretty much choose
int every time.

And because you can silently assign negative numbers to unsigned types,
it's not a good safeguard to ensure positive numbers. Unless you're
happy with large positive numbers...

Unsigned types are best for register contents, bits, masks, etc.


BR,
Jani.


>
> Regards,
> Madhav
>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 68f14d8f1e18..0d911a4adfaa 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -131,6 +131,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>>   
>>   /* intel_dsi.c */
>>   int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
>> +int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
>>   
>>   /* vlv_dsi.c */
>>   void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index fdeba8386d53..b0d8548f0462 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -512,21 +512,7 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>>   	u32 lp_to_hs_switch, hs_to_lp_switch;
>>   	u32 mul;
>>   
>> -	switch (intel_dsi->escape_clk_div) {
>> -	case 0:
>> -		tlpx_ns = 50;
>> -		break;
>> -	case 1:
>> -		tlpx_ns = 100;
>> -		break;
>> -
>> -	case 2:
>> -		tlpx_ns = 200;
>> -		break;
>> -	default:
>> -		tlpx_ns = 50;
>> -		break;
>> -	}
>> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
>>   
>>   	switch (intel_dsi->lane_count) {
>>   	case 1:
>

-- 
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Re: [PATCH v7 04/23] drm/i915/dsi: abstract intel_dsi_tlpx_ns()

[Madhav Chauhan]

On 10/16/2018 6:36 PM, Jani Nikula wrote:
> On Tue, 16 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>>> Will be needed in the future. No functional changes.
>> Agree, will be needing this while setting up DSI protocol timeouts for ICL.
>>
>>> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
>>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_dsi.c     | 13 +++++++++++++
>>>    drivers/gpu/drm/i915/intel_dsi.h     |  1 +
>>>    drivers/gpu/drm/i915/intel_dsi_vbt.c | 16 +---------------
>>>    3 files changed, 15 insertions(+), 15 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>> index 4daa1da94047..a32cc1f4b384 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>> @@ -15,3 +15,16 @@ int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
>>>    
>>>    	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
>>>    }
>>> +
>>> +int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
>>> +{
>>> +	switch (intel_dsi->escape_clk_div) {
>>> +	default:
>>> +	case 0:
>>> +		return 50;
>>> +	case 1:
>>> +		return 100;
>>> +	case 2:
>>> +		return 200;
>>> +	}
>>> +}
>> Can we change the return of this function to unsigned int, there is no way
>> that this function can return < 0  as per current implementation??
> I'd rather not. I'm sure I should be able to justify this exhaustively
> with examples, but I think gratuitous use of unsigned types leads to
> issues with integer promotions and signed/unsigned comparisons etc. So
> if it's "just a number", used for arithmetics, I'll pretty much choose
> int every time.
>
> And because you can silently assign negative numbers to unsigned types,
> it's not a good safeguard to ensure positive numbers. Unless you're
> happy with large positive numbers...
>
> Unsigned types are best for register contents, bits, masks, etc.

Agree with issues mentioned, i thought that should be case to case :),
but fine with uniform approach.
Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>

Regards,
Madhav

>
>
> BR,
> Jani.
>
>
>> Regards,
>> Madhav
>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>> index 68f14d8f1e18..0d911a4adfaa 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>> @@ -131,6 +131,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>>>    
>>>    /* intel_dsi.c */
>>>    int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
>>> +int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
>>>    
>>>    /* vlv_dsi.c */
>>>    void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> index fdeba8386d53..b0d8548f0462 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> @@ -512,21 +512,7 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>>>    	u32 lp_to_hs_switch, hs_to_lp_switch;
>>>    	u32 mul;
>>>    
>>> -	switch (intel_dsi->escape_clk_div) {
>>> -	case 0:
>>> -		tlpx_ns = 50;
>>> -		break;
>>> -	case 1:
>>> -		tlpx_ns = 100;
>>> -		break;
>>> -
>>> -	case 2:
>>> -		tlpx_ns = 200;
>>> -		break;
>>> -	default:
>>> -		tlpx_ns = 50;
>>> -		break;
>>> -	}
>>> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
>>>    
>>>    	switch (intel_dsi->lane_count) {
>>>    	case 1:

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[PATCH v7 05/23] drm/i915/icl: Make common DSI functions available

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch moves couple of legacy DSI functions to header and common DSI
files so that they can be re-used by Gen11 DSI. No functional change.

v2 by Jani:
 - Move intel_dsi_msleep() to intel_dsi_vbt.c

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.h     | 11 +++++++++++
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 11 +++++++++++
 drivers/gpu/drm/i915/vlv_dsi.c       | 21 ---------------------
 3 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 0d911a4adfaa..d7c0c599b52d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -129,6 +129,16 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 	return container_of(encoder, struct intel_dsi, base.base);
 }
 
+static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
+{
+	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
+}
+
+static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
+{
+	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
+}
+
 /* intel_dsi.c */
 int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
 int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
@@ -162,5 +172,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
 int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
 				 enum mipi_seq seq_id);
+void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
 
 #endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index b0d8548f0462..5e16b4c5f531 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -481,6 +481,17 @@ void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
 	}
 }
 
+void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
+	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
+		return;
+
+	msleep(msec);
+}
+
 int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
 {
 	struct intel_connector *connector = intel_dsi->attached_connector;
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index dbca30460a6b..ee0cd5d0bf91 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -290,16 +290,6 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
-static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
-{
-	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
-}
-
-static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
-{
-	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
-}
-
 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 				     struct intel_crtc_state *pipe_config,
 				     struct drm_connector_state *conn_state)
@@ -746,17 +736,6 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 			      const struct intel_crtc_state *pipe_config);
 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 
-static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
-{
-	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
-
-	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
-	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
-		return;
-
-	msleep(msec);
-}
-
 /*
  * Panel enable/disable sequences from the VBT spec.
  *
-- 
2.11.0

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Re: [PATCH v7 05/23] drm/i915/icl: Make common DSI functions available

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch moves couple of legacy DSI functions to header and common DSI
> files so that they can be re-used by Gen11 DSI. No functional change.
>
> v2 by Jani:
>   - Move intel_dsi_msleep() to intel_dsi_vbt.c

This will be used by icl dsi as well and and delay is directly passed
Shouldn't we have this inside intel_dsi.c??
Or
Because seq version from VBT is getting checked inside this function,
so that is taking the precedence??

Regards,
Madhav

> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dsi.h     | 11 +++++++++++
>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 11 +++++++++++
>   drivers/gpu/drm/i915/vlv_dsi.c       | 21 ---------------------
>   3 files changed, 22 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 0d911a4adfaa..d7c0c599b52d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -129,6 +129,16 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>   	return container_of(encoder, struct intel_dsi, base.base);
>   }
>   
> +static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
> +{
> +	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
> +}
> +
> +static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
> +{
> +	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
> +}
> +
>   /* intel_dsi.c */
>   int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
>   int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
> @@ -162,5 +172,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
>   int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
>   void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>   				 enum mipi_seq seq_id);
> +void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
>   
>   #endif /* _INTEL_DSI_H */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index b0d8548f0462..5e16b4c5f531 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -481,6 +481,17 @@ void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>   	}
>   }
>   
> +void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> +
> +	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
> +	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
> +		return;
> +
> +	msleep(msec);
> +}
> +
>   int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
>   {
>   	struct intel_connector *connector = intel_dsi->attached_connector;
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index dbca30460a6b..ee0cd5d0bf91 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -290,16 +290,6 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
>   	mutex_unlock(&dev_priv->sb_lock);
>   }
>   
> -static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
> -{
> -	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
> -}
> -
> -static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
> -{
> -	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
> -}
> -
>   static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>   				     struct intel_crtc_state *pipe_config,
>   				     struct drm_connector_state *conn_state)
> @@ -746,17 +736,6 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>   			      const struct intel_crtc_state *pipe_config);
>   static void intel_dsi_unprepare(struct intel_encoder *encoder);
>   
> -static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> -
> -	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
> -	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
> -		return;
> -
> -	msleep(msec);
> -}
> -
>   /*
>    * Panel enable/disable sequences from the VBT spec.
>    *

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Re: [PATCH v7 05/23] drm/i915/icl: Make common DSI functions available

[Jani Nikula]

On Tue, 16 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> This patch moves couple of legacy DSI functions to header and common DSI
>> files so that they can be re-used by Gen11 DSI. No functional change.
>>
>> v2 by Jani:
>>   - Move intel_dsi_msleep() to intel_dsi_vbt.c
>
> This will be used by icl dsi as well and and delay is directly passed
> Shouldn't we have this inside intel_dsi.c??
> Or
> Because seq version from VBT is getting checked inside this function,
> so that is taking the precedence??

I had it in intel_dsi.c at first, but decided on intel_dsi_vbt.c instead
because it does have a dependency on the VBT. And I presume on ICL this
will be a NOP due to v3+ sequence.

BR,
Jani.




>
> Regards,
> Madhav
>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi.h     | 11 +++++++++++
>>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 11 +++++++++++
>>   drivers/gpu/drm/i915/vlv_dsi.c       | 21 ---------------------
>>   3 files changed, 22 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 0d911a4adfaa..d7c0c599b52d 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -129,6 +129,16 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>>   	return container_of(encoder, struct intel_dsi, base.base);
>>   }
>>   
>> +static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
>> +{
>> +	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
>> +}
>> +
>> +static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
>> +{
>> +	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
>> +}
>> +
>>   /* intel_dsi.c */
>>   int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
>>   int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
>> @@ -162,5 +172,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
>>   int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
>>   void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>>   				 enum mipi_seq seq_id);
>> +void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
>>   
>>   #endif /* _INTEL_DSI_H */
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index b0d8548f0462..5e16b4c5f531 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -481,6 +481,17 @@ void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>>   	}
>>   }
>>   
>> +void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>> +
>> +	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
>> +	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
>> +		return;
>> +
>> +	msleep(msec);
>> +}
>> +
>>   int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
>>   {
>>   	struct intel_connector *connector = intel_dsi->attached_connector;
>> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
>> index dbca30460a6b..ee0cd5d0bf91 100644
>> --- a/drivers/gpu/drm/i915/vlv_dsi.c
>> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
>> @@ -290,16 +290,6 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
>>   	mutex_unlock(&dev_priv->sb_lock);
>>   }
>>   
>> -static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
>> -{
>> -	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
>> -}
>> -
>> -static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
>> -{
>> -	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
>> -}
>> -
>>   static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>>   				     struct intel_crtc_state *pipe_config,
>>   				     struct drm_connector_state *conn_state)
>> @@ -746,17 +736,6 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>>   			      const struct intel_crtc_state *pipe_config);
>>   static void intel_dsi_unprepare(struct intel_encoder *encoder);
>>   
>> -static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>> -{
>> -	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>> -
>> -	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
>> -	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
>> -		return;
>> -
>> -	msleep(msec);
>> -}
>> -
>>   /*
>>    * Panel enable/disable sequences from the VBT spec.
>>    *
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v7 05/23] drm/i915/icl: Make common DSI functions available

[Madhav Chauhan]

On 10/16/2018 6:09 PM, Jani Nikula wrote:
> On Tue, 16 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>>
>>> This patch moves couple of legacy DSI functions to header and common DSI
>>> files so that they can be re-used by Gen11 DSI. No functional change.
>>>
>>> v2 by Jani:
>>>    - Move intel_dsi_msleep() to intel_dsi_vbt.c
>> This will be used by icl dsi as well and and delay is directly passed
>> Shouldn't we have this inside intel_dsi.c??
>> Or
>> Because seq version from VBT is getting checked inside this function,
>> so that is taking the precedence??
> I had it in intel_dsi.c at first, but decided on intel_dsi_vbt.c instead
> because it does have a dependency on the VBT. And I presume on ICL this
> will be a NOP due to v3+ sequence.

Ok with this change. Thanks!!

Regards,
Madhav

>
> BR,
> Jani.
>
>
>
>
>> Regards,
>> Madhav
>>
>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_dsi.h     | 11 +++++++++++
>>>    drivers/gpu/drm/i915/intel_dsi_vbt.c | 11 +++++++++++
>>>    drivers/gpu/drm/i915/vlv_dsi.c       | 21 ---------------------
>>>    3 files changed, 22 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>> index 0d911a4adfaa..d7c0c599b52d 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>> @@ -129,6 +129,16 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>>>    	return container_of(encoder, struct intel_dsi, base.base);
>>>    }
>>>    
>>> +static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
>>> +{
>>> +	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
>>> +}
>>> +
>>> +static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
>>> +{
>>> +	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
>>> +}
>>> +
>>>    /* intel_dsi.c */
>>>    int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
>>>    int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
>>> @@ -162,5 +172,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
>>>    int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
>>>    void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>>>    				 enum mipi_seq seq_id);
>>> +void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
>>>    
>>>    #endif /* _INTEL_DSI_H */
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> index b0d8548f0462..5e16b4c5f531 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>> @@ -481,6 +481,17 @@ void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>>>    	}
>>>    }
>>>    
>>> +void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>>> +{
>>> +	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>>> +
>>> +	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
>>> +	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
>>> +		return;
>>> +
>>> +	msleep(msec);
>>> +}
>>> +
>>>    int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
>>>    {
>>>    	struct intel_connector *connector = intel_dsi->attached_connector;
>>> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
>>> index dbca30460a6b..ee0cd5d0bf91 100644
>>> --- a/drivers/gpu/drm/i915/vlv_dsi.c
>>> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
>>> @@ -290,16 +290,6 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
>>>    	mutex_unlock(&dev_priv->sb_lock);
>>>    }
>>>    
>>> -static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
>>> -{
>>> -	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
>>> -}
>>> -
>>> -static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
>>> -{
>>> -	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
>>> -}
>>> -
>>>    static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>>>    				     struct intel_crtc_state *pipe_config,
>>>    				     struct drm_connector_state *conn_state)
>>> @@ -746,17 +736,6 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>>>    			      const struct intel_crtc_state *pipe_config);
>>>    static void intel_dsi_unprepare(struct intel_encoder *encoder);
>>>    
>>> -static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>>> -{
>>> -	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>>> -
>>> -	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
>>> -	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
>>> -		return;
>>> -
>>> -	msleep(msec);
>>> -}
>>> -
>>>    /*
>>>     * Panel enable/disable sequences from the VBT spec.
>>>     *

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[PATCH v7 06/23] drm/i915/icl: Program DSI clock and data lane timing params

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.

v2: Use newly defined bitfields for data and clock lane

v3 by Jani:
 - Rebase on dphy abstraction
 - Reduce local variables
 - Remove unrelated comment changes (Ville)
 - Use the same style for range checks as VLV (Ville)
 - Assign, don't OR dphy_reg contents

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       |  18 ++++++
 drivers/gpu/drm/i915/intel_dsi.h     |   3 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 110 ++++++++++++++++++++++++++++++++++-
 3 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index ff5b285ca495..9602b6532028 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -291,6 +291,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		tmp |= intel_dsi->init_count;
 		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
 	}
+
+	/* Program DPHY clock lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+	}
+
+	/* Program DPHY data lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index d7c0c599b52d..12b758ebefce 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -85,6 +85,9 @@ struct intel_dsi {
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
+
+	/* data lanes dphy timing */
+	u32 dphy_data_lane_reg;
 	u32 video_frmt_cfg_bits;
 	u16 lp_byte_clk;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 5e16b4c5f531..3035422aa0d6 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -510,6 +510,111 @@ int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
 	return 1;
 }
 
+#define ICL_PREPARE_CNT_MAX	0x7
+#define ICL_CLK_ZERO_CNT_MAX	0xf
+#define ICL_TRAIL_CNT_MAX	0x7
+#define ICL_TCLK_PRE_CNT_MAX	0x3
+#define ICL_TCLK_POST_CNT_MAX	0x7
+#define ICL_HS_ZERO_CNT_MAX	0xf
+#define ICL_EXIT_ZERO_CNT_MAX	0x7
+
+static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	u32 tlpx_ns;
+	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+	u32 ths_prepare_ns, tclk_trail_ns;
+	u32 hs_zero_cnt;
+	u32 tclk_pre_cnt, tclk_post_cnt;
+
+	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
+
+	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+			     mipi_config->tclk_prepare);
+
+	/*
+	 * prepare cnt in escape clocks
+	 * this field represents a hexadecimal value with a precision
+	 * of 1.2 – i.e. the most significant bit is the integer
+	 * and the least significant 2 bits are fraction bits.
+	 * so, the field can represent a range of 0.25 to 1.75
+	 */
+	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
+		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
+		prepare_cnt = ICL_PREPARE_CNT_MAX;
+	}
+
+	/* clk zero count in escape clocks */
+	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
+				    ths_prepare_ns, tlpx_ns);
+	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
+		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
+	}
+
+	/* trail cnt in escape clocks*/
+	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
+	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
+		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
+		trail_cnt = ICL_TRAIL_CNT_MAX;
+	}
+
+	/* tclk pre count in escape clocks */
+	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
+	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
+		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
+		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
+	}
+
+	/* tclk post count in escape clocks */
+	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
+	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
+		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
+		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
+	}
+
+	/* hs zero cnt in escape clocks */
+	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
+				   ths_prepare_ns, tlpx_ns);
+	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
+		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
+	}
+
+	/* hs exit zero cnt in escape clocks */
+	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
+	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
+		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
+	}
+
+	/* clock lane dphy timings */
+	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
+			       CLK_PREPARE(prepare_cnt) |
+			       CLK_ZERO_OVERRIDE |
+			       CLK_ZERO(clk_zero_cnt) |
+			       CLK_PRE_OVERRIDE |
+			       CLK_PRE(tclk_pre_cnt) |
+			       CLK_POST_OVERRIDE |
+			       CLK_POST(tclk_post_cnt) |
+			       CLK_TRAIL_OVERRIDE |
+			       CLK_TRAIL(trail_cnt));
+
+	/* data lanes dphy timings */
+	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
+					 HS_PREPARE(prepare_cnt) |
+					 HS_ZERO_OVERRIDE |
+					 HS_ZERO(hs_zero_cnt) |
+					 HS_TRAIL_OVERRIDE |
+					 HS_TRAIL(trail_cnt) |
+					 HS_EXIT_OVERRIDE |
+					 HS_EXIT(exit_zero_cnt));
+}
+
 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -743,7 +848,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
 
-	vlv_dphy_param_init(intel_dsi);
+	if (IS_ICELAKE(dev_priv))
+		icl_dphy_param_init(intel_dsi);
+	else
+		vlv_dphy_param_init(intel_dsi);
 
 	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
 	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
-- 
2.11.0

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Re: [PATCH v7 06/23] drm/i915/icl: Program DSI clock and data lane timing params

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch programs D-PHY timing parameters for the
> clock and data lane (in escape clocks) of DSI
> controller (DSI port 0 and 1).
> These programmed timings would be used by DSI Controller
> to calculate link transition latencies of the data and
> clock lanes.
>
> v2: Use newly defined bitfields for data and clock lane
>
> v3 by Jani:
>   - Rebase on dphy abstraction
>   - Reduce local variables
>   - Remove unrelated comment changes (Ville)
>   - Use the same style for range checks as VLV (Ville)
>   - Assign, don't OR dphy_reg contents

v3 changes looks fine to me.

Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c       |  18 ++++++
>   drivers/gpu/drm/i915/intel_dsi.h     |   3 +
>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 110 ++++++++++++++++++++++++++++++++++-
>   3 files changed, 130 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index ff5b285ca495..9602b6532028 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -291,6 +291,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>   		tmp |= intel_dsi->init_count;
>   		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
>   	}
> +
> +	/* Program DPHY clock lanes timings */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +
> +		/* shadow register inside display core */
> +		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +	}
> +
> +	/* Program DPHY data lanes timings */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
> +			   intel_dsi->dphy_data_lane_reg);
> +
> +		/* shadow register inside display core */
> +		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
> +			   intel_dsi->dphy_data_lane_reg);
> +	}
>   }
>   
>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index d7c0c599b52d..12b758ebefce 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -85,6 +85,9 @@ struct intel_dsi {
>   	u32 port_bits;
>   	u32 bw_timer;
>   	u32 dphy_reg;
> +
> +	/* data lanes dphy timing */
> +	u32 dphy_data_lane_reg;
>   	u32 video_frmt_cfg_bits;
>   	u16 lp_byte_clk;
>   
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 5e16b4c5f531..3035422aa0d6 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -510,6 +510,111 @@ int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
>   	return 1;
>   }
>   
> +#define ICL_PREPARE_CNT_MAX	0x7
> +#define ICL_CLK_ZERO_CNT_MAX	0xf
> +#define ICL_TRAIL_CNT_MAX	0x7
> +#define ICL_TCLK_PRE_CNT_MAX	0x3
> +#define ICL_TCLK_POST_CNT_MAX	0x7
> +#define ICL_HS_ZERO_CNT_MAX	0xf
> +#define ICL_EXIT_ZERO_CNT_MAX	0x7
> +
> +static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> +{
> +	struct drm_device *dev = intel_dsi->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> +	u32 tlpx_ns;
> +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> +	u32 ths_prepare_ns, tclk_trail_ns;
> +	u32 hs_zero_cnt;
> +	u32 tclk_pre_cnt, tclk_post_cnt;
> +
> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
> +
> +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> +	ths_prepare_ns = max(mipi_config->ths_prepare,
> +			     mipi_config->tclk_prepare);
> +
> +	/*
> +	 * prepare cnt in escape clocks
> +	 * this field represents a hexadecimal value with a precision
> +	 * of 1.2 – i.e. the most significant bit is the integer
> +	 * and the least significant 2 bits are fraction bits.
> +	 * so, the field can represent a range of 0.25 to 1.75
> +	 */
> +	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> +	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
> +		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
> +		prepare_cnt = ICL_PREPARE_CNT_MAX;
> +	}
> +
> +	/* clk zero count in escape clocks */
> +	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
> +				    ths_prepare_ns, tlpx_ns);
> +	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
> +		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
> +	}
> +
> +	/* trail cnt in escape clocks*/
> +	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> +	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
> +		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
> +		trail_cnt = ICL_TRAIL_CNT_MAX;
> +	}
> +
> +	/* tclk pre count in escape clocks */
> +	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
> +	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
> +		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
> +		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
> +	}
> +
> +	/* tclk post count in escape clocks */
> +	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
> +	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
> +		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
> +		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
> +	}
> +
> +	/* hs zero cnt in escape clocks */
> +	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
> +				   ths_prepare_ns, tlpx_ns);
> +	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
> +		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
> +	}
> +
> +	/* hs exit zero cnt in escape clocks */
> +	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
> +	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
> +		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
> +	}
> +
> +	/* clock lane dphy timings */
> +	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
> +			       CLK_PREPARE(prepare_cnt) |
> +			       CLK_ZERO_OVERRIDE |
> +			       CLK_ZERO(clk_zero_cnt) |
> +			       CLK_PRE_OVERRIDE |
> +			       CLK_PRE(tclk_pre_cnt) |
> +			       CLK_POST_OVERRIDE |
> +			       CLK_POST(tclk_post_cnt) |
> +			       CLK_TRAIL_OVERRIDE |
> +			       CLK_TRAIL(trail_cnt));
> +
> +	/* data lanes dphy timings */
> +	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
> +					 HS_PREPARE(prepare_cnt) |
> +					 HS_ZERO_OVERRIDE |
> +					 HS_ZERO(hs_zero_cnt) |
> +					 HS_TRAIL_OVERRIDE |
> +					 HS_TRAIL(trail_cnt) |
> +					 HS_EXIT_OVERRIDE |
> +					 HS_EXIT(exit_zero_cnt));
> +}
> +
>   static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>   {
>   	struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -743,7 +848,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   
>   	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>   
> -	vlv_dphy_param_init(intel_dsi);
> +	if (IS_ICELAKE(dev_priv))
> +		icl_dphy_param_init(intel_dsi);
> +	else
> +		vlv_dphy_param_init(intel_dsi);
>   
>   	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
>   	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);

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[PATCH v7 07/23] drm/i915/icl: Program TA_TIMING_PARAM registers

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).

v2: Changes
    - Don't use KHz() macro (Ville/Jani N)
    - Use newly defined bitfields

v3 by Jani:
 - Use intel_dsi_bitrate() in favor of a new field
 - Remove redundant parens

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9602b6532028..f9df3a7fa66b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -309,6 +309,27 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
 			   intel_dsi->dphy_data_lane_reg);
 	}
+
+	/*
+	 * If DSI link operating at or below an 800 MHz,
+	 * TA_SURE should be override and programmed to
+	 * a value '0' inside TA_PARAM_REGISTERS otherwise
+	 * leave all fields at HW default values.
+	 */
+	if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_MASK;
+			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+			/* shadow register inside display core */
+			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_MASK;
+			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+		}
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
-- 
2.11.0

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Re: [PATCH v7 07/23] drm/i915/icl: Program TA_TIMING_PARAM registers

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch programs D-PHY timing parameters for the
> bus turn around flow(in escape clocks) only if dsi link
> frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
> identical register DSI_TA_TIMING_PARAM (inside DSI
> Controller within the Display Core).
>
> v2: Changes
>      - Don't use KHz() macro (Ville/Jani N)
>      - Use newly defined bitfields
>
> v3 by Jani:
>   - Use intel_dsi_bitrate() in favor of a new field
>   - Remove redundant parens

v3 changes looks fine to me.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 9602b6532028..f9df3a7fa66b 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -309,6 +309,27 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>   		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
>   			   intel_dsi->dphy_data_lane_reg);
>   	}
> +
> +	/*
> +	 * If DSI link operating at or below an 800 MHz,
> +	 * TA_SURE should be override and programmed to
> +	 * a value '0' inside TA_PARAM_REGISTERS otherwise
> +	 * leave all fields at HW default values.
> +	 */
> +	if (intel_dsi_bitrate(intel_dsi) <= 800000) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
> +			tmp &= ~TA_SURE_MASK;
> +			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
> +			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
> +
> +			/* shadow register inside display core */
> +			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
> +			tmp &= ~TA_SURE_MASK;
> +			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
> +			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> +		}
> +	}
>   }
>   
>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)

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[PATCH v7 08/23] drm/i915/icl: Get DSI transcoder for a given port

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 8 ++++++++
 drivers/gpu/drm/i915/intel_display.h | 6 ++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f9df3a7fa66b..407c3065d08d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,6 +27,14 @@
 
 #include "intel_dsi.h"
 
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(enum port port)
+{
+	if (port == PORT_A)
+		return TRANSCODER_DSI_0;
+	else
+		return TRANSCODER_DSI_1;
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 9fac67e31205..54087130f67e 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -61,8 +61,10 @@ enum transcoder {
 	TRANSCODER_B,
 	TRANSCODER_C,
 	TRANSCODER_EDP,
-	TRANSCODER_DSI_A,
-	TRANSCODER_DSI_C,
+	TRANSCODER_DSI_0,
+	TRANSCODER_DSI_1,
+	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
+	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
 
 	I915_MAX_TRANSCODERS
 };
-- 
2.11.0

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[PATCH v7 09/23] drm/i915/icl: Add macros for MMIO of DSI transcoder registers

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch adds _MMIO_DSI macros for accessing DSI
transcoder registers.

v2: Use _MMIO_TRANS() (Ville)

Credits-to: Jani N

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e13e51fee47..436ff68b6b18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9795,6 +9795,10 @@ enum skl_power_gate {
 #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
 
+/* Gen11 DSI */
+#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
+						    dsi0, dsi1)
+
 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
-- 
2.11.0

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[PATCH v7 10/23] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.

v2: Changes (Jani N)
    - Define _SHIFT and _MASK for bitfields
    - Define values for fields already shifted in place

v3 by Jani:
 - Fix _SHIFT fields copy-pasted from _MASK
 - Indentation fixes
 - Reduce S3D orientation to single macro
 - Wrap a macro parameter in parens

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 45 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 436ff68b6b18..b065e4ca0b45 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10379,6 +10379,51 @@ enum skl_power_gate {
 #define  TA_GET_MASK			(0xf << 0)
 #define  TA_GET_SHIFT			0
 
+/* DSI transcoder configuration */
+#define _DSI_TRANS_FUNC_CONF_0		0x6b030
+#define _DSI_TRANS_FUNC_CONF_1		0x6b830
+#define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
+						  _DSI_TRANS_FUNC_CONF_0,\
+						  _DSI_TRANS_FUNC_CONF_1)
+#define  OP_MODE_MASK			(0x3 << 28)
+#define  OP_MODE_SHIFT			28
+#define  CMD_MODE_NO_GATE		(0x0 << 28)
+#define  CMD_MODE_TE_GATE		(0x1 << 28)
+#define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
+#define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
+#define  LINK_READY			(1 << 20)
+#define  PIX_FMT_MASK			(0x3 << 16)
+#define  PIX_FMT_SHIFT			16
+#define  PIX_FMT_RGB565			(0x0 << 16)
+#define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
+#define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
+#define  PIX_FMT_RGB888			(0x3 << 16)
+#define  PIX_FMT_RGB101010		(0x4 << 16)
+#define  PIX_FMT_RGB121212		(0x5 << 16)
+#define  PIX_FMT_COMPRESSED		(0x6 << 16)
+#define  BGR_TRANSMISSION		(1 << 15)
+#define  PIX_VIRT_CHAN(x)		((x) << 12)
+#define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
+#define  PIX_VIRT_CHAN_SHIFT		12
+#define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
+#define  PIX_BUF_THRESHOLD_SHIFT	10
+#define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
+#define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
+#define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
+#define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
+#define  CONTINUOUS_CLK_MASK		(0x3 << 8)
+#define  CONTINUOUS_CLK_SHIFT		8
+#define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
+#define  CLK_HS_OR_LP			(0x2 << 8)
+#define  CLK_HS_CONTINUOUS		(0x3 << 8)
+#define  LINK_CALIBRATION_MASK		(0x3 << 4)
+#define  LINK_CALIBRATION_SHIFT		4
+#define  CALIBRATION_DISABLED		(0x0 << 4)
+#define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
+#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
+#define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
+#define  EOTP_DISABLED			(1 << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.11.0

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Re: [PATCH v7 10/23] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines transcoder function configuration
> registers and its bitfields for both DSI ports.
> Used while programming/enabling DSI transcoder.
>
> v2: Changes (Jani N)
>      - Define _SHIFT and _MASK for bitfields
>      - Define values for fields already shifted in place
>
> v3 by Jani:
>   - Fix _SHIFT fields copy-pasted from _MASK
>   - Indentation fixes
>   - Reduce S3D orientation to single macro
>   - Wrap a macro parameter in parens

v3 changes looks fine.

Regards,
Madhav

> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 45 +++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 436ff68b6b18..b065e4ca0b45 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10379,6 +10379,51 @@ enum skl_power_gate {
>   #define  TA_GET_MASK			(0xf << 0)
>   #define  TA_GET_SHIFT			0
>   
> +/* DSI transcoder configuration */
> +#define _DSI_TRANS_FUNC_CONF_0		0x6b030
> +#define _DSI_TRANS_FUNC_CONF_1		0x6b830
> +#define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
> +						  _DSI_TRANS_FUNC_CONF_0,\
> +						  _DSI_TRANS_FUNC_CONF_1)
> +#define  OP_MODE_MASK			(0x3 << 28)
> +#define  OP_MODE_SHIFT			28
> +#define  CMD_MODE_NO_GATE		(0x0 << 28)
> +#define  CMD_MODE_TE_GATE		(0x1 << 28)
> +#define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
> +#define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
> +#define  LINK_READY			(1 << 20)
> +#define  PIX_FMT_MASK			(0x3 << 16)
> +#define  PIX_FMT_SHIFT			16
> +#define  PIX_FMT_RGB565			(0x0 << 16)
> +#define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
> +#define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
> +#define  PIX_FMT_RGB888			(0x3 << 16)
> +#define  PIX_FMT_RGB101010		(0x4 << 16)
> +#define  PIX_FMT_RGB121212		(0x5 << 16)
> +#define  PIX_FMT_COMPRESSED		(0x6 << 16)
> +#define  BGR_TRANSMISSION		(1 << 15)
> +#define  PIX_VIRT_CHAN(x)		((x) << 12)
> +#define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
> +#define  PIX_VIRT_CHAN_SHIFT		12
> +#define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
> +#define  PIX_BUF_THRESHOLD_SHIFT	10
> +#define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
> +#define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
> +#define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
> +#define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
> +#define  CONTINUOUS_CLK_MASK		(0x3 << 8)
> +#define  CONTINUOUS_CLK_SHIFT		8
> +#define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
> +#define  CLK_HS_OR_LP			(0x2 << 8)
> +#define  CLK_HS_CONTINUOUS		(0x3 << 8)
> +#define  LINK_CALIBRATION_MASK		(0x3 << 4)
> +#define  LINK_CALIBRATION_SHIFT		4
> +#define  CALIBRATION_DISABLED		(0x0 << 4)
> +#define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
> +#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
> +#define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
> +#define  EOTP_DISABLED			(1 << 0)
> +
>   /* bits 31:0 */
>   #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>   #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

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[PATCH v7 11/23] drm/i915/icl: Configure DSI transcoders

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.

v2: Rebase
v3: Use newly defined bitfields.

v4 by Jani:
 - Use intel_dsi_bitrate()
 - Make bgr_enabled bool
 - Use 0 instead of 0x0
 - Replace DRM_ERROR() with MISSING_CASE() on pixel format and video mode
 - Use is_vid_mode()

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 87 +++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dsi.h     |  3 ++
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
 3 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 407c3065d08d..756c75d0c86c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,7 +27,7 @@
 
 #include "intel_dsi.h"
 
-static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(enum port port)
+static enum transcoder dsi_port_to_transcoder(enum port port)
 {
 	if (port == PORT_A)
 		return TRANSCODER_DSI_0;
@@ -340,6 +340,88 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+	enum transcoder dsi_trans;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+
+		if (intel_dsi->eotp_pkt)
+			tmp &= ~EOTP_DISABLED;
+		else
+			tmp |= EOTP_DISABLED;
+
+		/* enable link calibration if freq > 1.5Gbps */
+		if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
+			tmp &= ~LINK_CALIBRATION_MASK;
+			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
+		}
+
+		/* configure continuous clock */
+		tmp &= ~CONTINUOUS_CLK_MASK;
+		if (intel_dsi->clock_stop)
+			tmp |= CLK_ENTER_LP_AFTER_DATA;
+		else
+			tmp |= CLK_HS_CONTINUOUS;
+
+		/* configure buffer threshold limit to minimum */
+		tmp &= ~PIX_BUF_THRESHOLD_MASK;
+		tmp |= PIX_BUF_THRESHOLD_1_4;
+
+		/* set virtual channel to '0' */
+		tmp &= ~PIX_VIRT_CHAN_MASK;
+		tmp |= PIX_VIRT_CHAN(0);
+
+		/* program BGR transmission */
+		if (intel_dsi->bgr_enabled)
+			tmp |= BGR_TRANSMISSION;
+
+		/* select pixel format */
+		tmp &= ~PIX_FMT_MASK;
+		switch (intel_dsi->pixel_format) {
+		default:
+			MISSING_CASE(intel_dsi->pixel_format);
+			/* fallthrough */
+		case MIPI_DSI_FMT_RGB565:
+			tmp |= PIX_FMT_RGB565;
+			break;
+		case MIPI_DSI_FMT_RGB666_PACKED:
+			tmp |= PIX_FMT_RGB666_PACKED;
+			break;
+		case MIPI_DSI_FMT_RGB666:
+			tmp |= PIX_FMT_RGB666_LOOSE;
+			break;
+		case MIPI_DSI_FMT_RGB888:
+			tmp |= PIX_FMT_RGB888;
+			break;
+		}
+
+		/* program DSI operation mode */
+		if (is_vid_mode(intel_dsi)) {
+			tmp &= ~OP_MODE_MASK;
+			switch (intel_dsi->video_mode_format) {
+			default:
+				MISSING_CASE(intel_dsi->video_mode_format);
+				/* fallthrough */
+			case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
+				tmp |= VIDEO_MODE_SYNC_EVENT;
+				break;
+			case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
+				tmp |= VIDEO_MODE_SYNC_PULSE;
+				break;
+			}
+		}
+
+		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -356,6 +438,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
+
+	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
+	gen11_dsi_configure_transcoder(encoder);
 }
 
 static void __attribute__((unused))
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 12b758ebefce..14567929de9a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -81,6 +81,9 @@ struct intel_dsi {
 	u16 dcs_backlight_ports;
 	u16 dcs_cabc_ports;
 
+	/* RGB or BGR */
+	bool bgr_enabled;
+
 	u8 pixel_overlap;
 	u32 port_bits;
 	u32 bw_timer;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 3035422aa0d6..cca071406c25 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -805,6 +805,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 	intel_dsi->video_frmt_cfg_bits =
 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
+	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
 
 	/* Starting point, adjusted depending on dual link and burst mode */
 	intel_dsi->pclk = mode->clock;
-- 
2.11.0

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Re: [PATCH v7 11/23] drm/i915/icl: Configure DSI transcoders

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch programs DSI operation mode, pixel format,
> BGR info, link calibration etc for the DSI transcoder.
> This patch also extract BGR info of the DSI panel from
> VBT and save it inside struct intel_dsi which used for
> configuring DSI transcoder.
>
> v2: Rebase
> v3: Use newly defined bitfields.
>
> v4 by Jani:
>   - Use intel_dsi_bitrate()
>   - Make bgr_enabled bool
>   - Use 0 instead of 0x0
>   - Replace DRM_ERROR() with MISSING_CASE() on pixel format and video mode
>   - Use is_vid_mode()

v4 changes are fine.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c       | 87 +++++++++++++++++++++++++++++++++++-
>   drivers/gpu/drm/i915/intel_dsi.h     |  3 ++
>   drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
>   3 files changed, 90 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 407c3065d08d..756c75d0c86c 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -27,7 +27,7 @@
>   
>   #include "intel_dsi.h"
>   
> -static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(enum port port)
> +static enum transcoder dsi_port_to_transcoder(enum port port)
>   {
>   	if (port == PORT_A)
>   		return TRANSCODER_DSI_0;
> @@ -340,6 +340,88 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>   	}
>   }
>   
> +static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +	enum transcoder dsi_trans;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
> +
> +		if (intel_dsi->eotp_pkt)
> +			tmp &= ~EOTP_DISABLED;
> +		else
> +			tmp |= EOTP_DISABLED;
> +
> +		/* enable link calibration if freq > 1.5Gbps */
> +		if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
> +			tmp &= ~LINK_CALIBRATION_MASK;
> +			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
> +		}
> +
> +		/* configure continuous clock */
> +		tmp &= ~CONTINUOUS_CLK_MASK;
> +		if (intel_dsi->clock_stop)
> +			tmp |= CLK_ENTER_LP_AFTER_DATA;
> +		else
> +			tmp |= CLK_HS_CONTINUOUS;
> +
> +		/* configure buffer threshold limit to minimum */
> +		tmp &= ~PIX_BUF_THRESHOLD_MASK;
> +		tmp |= PIX_BUF_THRESHOLD_1_4;
> +
> +		/* set virtual channel to '0' */
> +		tmp &= ~PIX_VIRT_CHAN_MASK;
> +		tmp |= PIX_VIRT_CHAN(0);
> +
> +		/* program BGR transmission */
> +		if (intel_dsi->bgr_enabled)
> +			tmp |= BGR_TRANSMISSION;
> +
> +		/* select pixel format */
> +		tmp &= ~PIX_FMT_MASK;
> +		switch (intel_dsi->pixel_format) {
> +		default:
> +			MISSING_CASE(intel_dsi->pixel_format);
> +			/* fallthrough */
> +		case MIPI_DSI_FMT_RGB565:
> +			tmp |= PIX_FMT_RGB565;
> +			break;
> +		case MIPI_DSI_FMT_RGB666_PACKED:
> +			tmp |= PIX_FMT_RGB666_PACKED;
> +			break;
> +		case MIPI_DSI_FMT_RGB666:
> +			tmp |= PIX_FMT_RGB666_LOOSE;
> +			break;
> +		case MIPI_DSI_FMT_RGB888:
> +			tmp |= PIX_FMT_RGB888;
> +			break;
> +		}
> +
> +		/* program DSI operation mode */
> +		if (is_vid_mode(intel_dsi)) {
> +			tmp &= ~OP_MODE_MASK;
> +			switch (intel_dsi->video_mode_format) {
> +			default:
> +				MISSING_CASE(intel_dsi->video_mode_format);
> +				/* fallthrough */
> +			case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
> +				tmp |= VIDEO_MODE_SYNC_EVENT;
> +				break;
> +			case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
> +				tmp |= VIDEO_MODE_SYNC_PULSE;
> +				break;
> +			}
> +		}
> +
> +		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> +	}
> +}
> +
>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>   {
>   	/* step 4a: power up all lanes of the DDI used by DSI */
> @@ -356,6 +438,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>   
>   	/* setup D-PHY timings */
>   	gen11_dsi_setup_dphy_timings(encoder);
> +
> +	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> +	gen11_dsi_configure_transcoder(encoder);
>   }
>   
>   static void __attribute__((unused))
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 12b758ebefce..14567929de9a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -81,6 +81,9 @@ struct intel_dsi {
>   	u16 dcs_backlight_ports;
>   	u16 dcs_cabc_ports;
>   
> +	/* RGB or BGR */
> +	bool bgr_enabled;
> +
>   	u8 pixel_overlap;
>   	u32 port_bits;
>   	u32 bw_timer;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 3035422aa0d6..cca071406c25 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -805,6 +805,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
>   	intel_dsi->video_frmt_cfg_bits =
>   		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
> +	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
>   
>   	/* Starting point, adjusted depending on dual link and burst mode */
>   	intel_dsi->pclk = mode->clock;

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Re: [PATCH v7 11/23] drm/i915/icl: Configure DSI transcoders

[Jani Nikula]

On Sat, 20 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> This patch programs DSI operation mode, pixel format,
>> BGR info, link calibration etc for the DSI transcoder.
>> This patch also extract BGR info of the DSI panel from
>> VBT and save it inside struct intel_dsi which used for
>> configuring DSI transcoder.
>>
>> v2: Rebase
>> v3: Use newly defined bitfields.
>>
>> v4 by Jani:
>>   - Use intel_dsi_bitrate()
>>   - Make bgr_enabled bool
>>   - Use 0 instead of 0x0
>>   - Replace DRM_ERROR() with MISSING_CASE() on pixel format and video mode
>>   - Use is_vid_mode()
>
> v4 changes are fine.

Thanks for double-checking; I think just confirming that is fine. Pushed
up to and including this patch.

BR,
Jani.



>
> Regards,
> Madhav
>
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>   drivers/gpu/drm/i915/icl_dsi.c       | 87 +++++++++++++++++++++++++++++++++++-
>>   drivers/gpu/drm/i915/intel_dsi.h     |  3 ++
>>   drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
>>   3 files changed, 90 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index 407c3065d08d..756c75d0c86c 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -27,7 +27,7 @@
>>   
>>   #include "intel_dsi.h"
>>   
>> -static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(enum port port)
>> +static enum transcoder dsi_port_to_transcoder(enum port port)
>>   {
>>   	if (port == PORT_A)
>>   		return TRANSCODER_DSI_0;
>> @@ -340,6 +340,88 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>>   	}
>>   }
>>   
>> +static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +	u32 tmp;
>> +	enum port port;
>> +	enum transcoder dsi_trans;
>> +
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		dsi_trans = dsi_port_to_transcoder(port);
>> +		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
>> +
>> +		if (intel_dsi->eotp_pkt)
>> +			tmp &= ~EOTP_DISABLED;
>> +		else
>> +			tmp |= EOTP_DISABLED;
>> +
>> +		/* enable link calibration if freq > 1.5Gbps */
>> +		if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
>> +			tmp &= ~LINK_CALIBRATION_MASK;
>> +			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
>> +		}
>> +
>> +		/* configure continuous clock */
>> +		tmp &= ~CONTINUOUS_CLK_MASK;
>> +		if (intel_dsi->clock_stop)
>> +			tmp |= CLK_ENTER_LP_AFTER_DATA;
>> +		else
>> +			tmp |= CLK_HS_CONTINUOUS;
>> +
>> +		/* configure buffer threshold limit to minimum */
>> +		tmp &= ~PIX_BUF_THRESHOLD_MASK;
>> +		tmp |= PIX_BUF_THRESHOLD_1_4;
>> +
>> +		/* set virtual channel to '0' */
>> +		tmp &= ~PIX_VIRT_CHAN_MASK;
>> +		tmp |= PIX_VIRT_CHAN(0);
>> +
>> +		/* program BGR transmission */
>> +		if (intel_dsi->bgr_enabled)
>> +			tmp |= BGR_TRANSMISSION;
>> +
>> +		/* select pixel format */
>> +		tmp &= ~PIX_FMT_MASK;
>> +		switch (intel_dsi->pixel_format) {
>> +		default:
>> +			MISSING_CASE(intel_dsi->pixel_format);
>> +			/* fallthrough */
>> +		case MIPI_DSI_FMT_RGB565:
>> +			tmp |= PIX_FMT_RGB565;
>> +			break;
>> +		case MIPI_DSI_FMT_RGB666_PACKED:
>> +			tmp |= PIX_FMT_RGB666_PACKED;
>> +			break;
>> +		case MIPI_DSI_FMT_RGB666:
>> +			tmp |= PIX_FMT_RGB666_LOOSE;
>> +			break;
>> +		case MIPI_DSI_FMT_RGB888:
>> +			tmp |= PIX_FMT_RGB888;
>> +			break;
>> +		}
>> +
>> +		/* program DSI operation mode */
>> +		if (is_vid_mode(intel_dsi)) {
>> +			tmp &= ~OP_MODE_MASK;
>> +			switch (intel_dsi->video_mode_format) {
>> +			default:
>> +				MISSING_CASE(intel_dsi->video_mode_format);
>> +				/* fallthrough */
>> +			case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
>> +				tmp |= VIDEO_MODE_SYNC_EVENT;
>> +				break;
>> +			case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
>> +				tmp |= VIDEO_MODE_SYNC_PULSE;
>> +				break;
>> +			}
>> +		}
>> +
>> +		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
>> +	}
>> +}
>> +
>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   {
>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>> @@ -356,6 +438,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   
>>   	/* setup D-PHY timings */
>>   	gen11_dsi_setup_dphy_timings(encoder);
>> +
>> +	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> +	gen11_dsi_configure_transcoder(encoder);
>>   }
>>   
>>   static void __attribute__((unused))
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 12b758ebefce..14567929de9a 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -81,6 +81,9 @@ struct intel_dsi {
>>   	u16 dcs_backlight_ports;
>>   	u16 dcs_cabc_ports;
>>   
>> +	/* RGB or BGR */
>> +	bool bgr_enabled;
>> +
>>   	u8 pixel_overlap;
>>   	u32 port_bits;
>>   	u32 bw_timer;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index 3035422aa0d6..cca071406c25 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -805,6 +805,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
>>   	intel_dsi->video_frmt_cfg_bits =
>>   		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
>> +	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
>>   
>>   	/* Starting point, adjusted depending on dual link and burst mode */
>>   	intel_dsi->pclk = mode->clock;
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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[PATCH v7 12/23] drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.

v2: Changes:
    - Remove redundant extra line
    - Correct some of bitfield definition

v3 by Jani:
 - Move DSI transcoder offsets to GEN11_FEATURES

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c |  3 +++
 drivers/gpu/drm/i915/i915_reg.h | 17 +++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0a05cc7ace14..b86b735a8634 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = {
 
 #define GEN11_FEATURES \
 	GEN10_FEATURES, \
+	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
+			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
+			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
 	GEN(11), \
 	.ddb_size = 2048, \
 	.has_logical_ring_elsq = 1
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b065e4ca0b45..79e633c1e9ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4066,6 +4066,8 @@ enum {
 #define TRANSCODER_C_OFFSET 0x62000
 #define CHV_TRANSCODER_C_OFFSET 0x63000
 #define TRANSCODER_EDP_OFFSET 0x6f000
+#define TRANSCODER_DSI0_OFFSET	0x6b000
+#define TRANSCODER_DSI1_OFFSET	0x6b800
 
 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
 	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
@@ -9021,6 +9023,8 @@ enum skl_power_gate {
 #define _TRANS_DDI_FUNC_CTL_B		0x61400
 #define _TRANS_DDI_FUNC_CTL_C		0x62400
 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
+#define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
+#define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
 
 #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
@@ -9058,6 +9062,19 @@ enum skl_power_gate {
 					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
 					| TRANS_DDI_HDMI_SCRAMBLING)
 
+#define _TRANS_DDI_FUNC_CTL2_A		0x60404
+#define _TRANS_DDI_FUNC_CTL2_B		0x61404
+#define _TRANS_DDI_FUNC_CTL2_C		0x62404
+#define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
+#define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
+#define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
+#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
+						     _TRANS_DDI_FUNC_CTL2_A)
+#define  PORT_SYNC_MODE_ENABLE			(1 << 4)
+#define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) < 0)
+#define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)
+#define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0
+
 /* DisplayPort Transport Control */
 #define _DP_TP_CTL_A			0x64040
 #define _DP_TP_CTL_B			0x64140
-- 
2.11.0

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Re: [PATCH v7 12/23] drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
> registers and their bitfields for DSI. These registers are used
> for enabling port sync mode, input pipe select, data lane width
> configuration etc.
>
> v2: Changes:
>      - Remove redundant extra line
>      - Correct some of bitfield definition
>
> v3 by Jani:
>   - Move DSI transcoder offsets to GEN11_FEATURES

v3 changes looks fine.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c |  3 +++
>   drivers/gpu/drm/i915/i915_reg.h | 17 +++++++++++++++++
>   2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 0a05cc7ace14..b86b735a8634 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = {
>   
>   #define GEN11_FEATURES \
>   	GEN10_FEATURES, \
> +	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> +			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
> +			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
>   	GEN(11), \
>   	.ddb_size = 2048, \
>   	.has_logical_ring_elsq = 1
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b065e4ca0b45..79e633c1e9ad 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4066,6 +4066,8 @@ enum {
>   #define TRANSCODER_C_OFFSET 0x62000
>   #define CHV_TRANSCODER_C_OFFSET 0x63000
>   #define TRANSCODER_EDP_OFFSET 0x6f000
> +#define TRANSCODER_DSI0_OFFSET	0x6b000
> +#define TRANSCODER_DSI1_OFFSET	0x6b800
>   
>   #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
>   	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
> @@ -9021,6 +9023,8 @@ enum skl_power_gate {
>   #define _TRANS_DDI_FUNC_CTL_B		0x61400
>   #define _TRANS_DDI_FUNC_CTL_C		0x62400
>   #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
> +#define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
> +#define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
>   #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
>   
>   #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
> @@ -9058,6 +9062,19 @@ enum skl_power_gate {
>   					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
>   					| TRANS_DDI_HDMI_SCRAMBLING)
>   
> +#define _TRANS_DDI_FUNC_CTL2_A		0x60404
> +#define _TRANS_DDI_FUNC_CTL2_B		0x61404
> +#define _TRANS_DDI_FUNC_CTL2_C		0x62404
> +#define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
> +#define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
> +#define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
> +#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
> +						     _TRANS_DDI_FUNC_CTL2_A)
> +#define  PORT_SYNC_MODE_ENABLE			(1 << 4)
> +#define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) < 0)
> +#define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)
> +#define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0
> +
>   /* DisplayPort Transport Control */
>   #define _DP_TP_CTL_A			0x64040
>   #define _DP_TP_CTL_B			0x64140

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[PATCH v7 13/23] drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch select input PIPE for DSI, data lanes width,
enable port sync mode and wait for DSI link to become ready.

v2 by Jani:
 - Use MISSING_CASE with fallthrough instead of DRM_ERROR
 - minor stylistic changes

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 64 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 60 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 756c75d0c86c..87d5e6435791 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -340,10 +340,14 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	}
 }
 
-static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+static void
+gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	enum pipe pipe = intel_crtc->pipe;
 	u32 tmp;
 	enum port port;
 	enum transcoder dsi_trans;
@@ -420,9 +424,61 @@ static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
 
 		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 	}
+
+	/* enable port sync mode if dual link */
+	if (intel_dsi->dual_link) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
+			tmp |= PORT_SYNC_MODE_ENABLE;
+			I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
+		}
+
+		//TODO: configure DSS_CTL1
+	}
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+
+		/* select data lane width */
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+		tmp &= ~DDI_PORT_WIDTH_MASK;
+		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+
+		/* select input pipe */
+		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
+		switch (pipe) {
+		default:
+			MISSING_CASE(pipe);
+			/* fallthrough */
+		case PIPE_A:
+			tmp |= TRANS_DDI_EDP_INPUT_A_ON;
+			break;
+		case PIPE_B:
+			tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+			break;
+		case PIPE_C:
+			tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+			break;
+		}
+
+		/* enable DDI buffer */
+		tmp |= TRANS_DDI_FUNC_ENABLE;
+		I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
+	}
+
+	/* wait for link ready */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
+				LINK_READY), 2500))
+			DRM_ERROR("DSI link not ready\n");
+	}
 }
 
-static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
+static void
+gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *pipe_config)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
@@ -440,7 +496,7 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 	gen11_dsi_setup_dphy_timings(encoder);
 
 	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
-	gen11_dsi_configure_transcoder(encoder);
+	gen11_dsi_configure_transcoder(encoder, pipe_config);
 }
 
 static void __attribute__((unused))
@@ -455,5 +511,5 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 	gen11_dsi_program_esc_clk_div(encoder);
 
 	/* step4: enable DSI port and DPHY */
-	gen11_dsi_enable_port_and_phy(encoder);
+	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
 }
-- 
2.11.0

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Re: [PATCH v7 13/23] drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch select input PIPE for DSI, data lanes width,
> enable port sync mode and wait for DSI link to become ready.
>
> v2 by Jani:
>   - Use MISSING_CASE with fallthrough instead of DRM_ERROR
>   - minor stylistic changes

v2 changes are good.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 64 +++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 60 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 756c75d0c86c..87d5e6435791 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -340,10 +340,14 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>   	}
>   }
>   
> -static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
> +static void
> +gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> +			       const struct intel_crtc_state *pipe_config)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	enum pipe pipe = intel_crtc->pipe;
>   	u32 tmp;
>   	enum port port;
>   	enum transcoder dsi_trans;
> @@ -420,9 +424,61 @@ static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
>   
>   		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
>   	}
> +
> +	/* enable port sync mode if dual link */
> +	if (intel_dsi->dual_link) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			dsi_trans = dsi_port_to_transcoder(port);
> +			tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
> +			tmp |= PORT_SYNC_MODE_ENABLE;
> +			I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
> +		}
> +
> +		//TODO: configure DSS_CTL1
> +	}
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +
> +		/* select data lane width */
> +		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> +		tmp &= ~DDI_PORT_WIDTH_MASK;
> +		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
> +
> +		/* select input pipe */
> +		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
> +		switch (pipe) {
> +		default:
> +			MISSING_CASE(pipe);
> +			/* fallthrough */
> +		case PIPE_A:
> +			tmp |= TRANS_DDI_EDP_INPUT_A_ON;
> +			break;
> +		case PIPE_B:
> +			tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
> +			break;
> +		case PIPE_C:
> +			tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
> +			break;
> +		}
> +
> +		/* enable DDI buffer */
> +		tmp |= TRANS_DDI_FUNC_ENABLE;
> +		I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
> +	}
> +
> +	/* wait for link ready */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
> +				LINK_READY), 2500))
> +			DRM_ERROR("DSI link not ready\n");
> +	}
>   }
>   
> -static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> +static void
> +gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *pipe_config)
>   {
>   	/* step 4a: power up all lanes of the DDI used by DSI */
>   	gen11_dsi_power_up_lanes(encoder);
> @@ -440,7 +496,7 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>   	gen11_dsi_setup_dphy_timings(encoder);
>   
>   	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> -	gen11_dsi_configure_transcoder(encoder);
> +	gen11_dsi_configure_transcoder(encoder, pipe_config);
>   }
>   
>   static void __attribute__((unused))
> @@ -455,5 +511,5 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
>   	gen11_dsi_program_esc_clk_div(encoder);
>   
>   	/* step4: enable DSI port and DPHY */
> -	gen11_dsi_enable_port_and_phy(encoder);
> +	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
>   }

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[PATCH v7 14/23] drm/i915/icl: Define DSI transcoder timing registers

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch defines registers and bitfields used for
programming DSI transcoder's horizontal and vertical
timings.

v2: Remove TRANS_TIMING_SHIFT definition

v3 by Jani:
 - Group macros by transcoder

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 79e633c1e9ad..c4270ca26a11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4061,6 +4061,20 @@ enum {
 #define _VSYNCSHIFT_B	0x61028
 #define _PIPE_MULT_B	0x6102c
 
+/* DSI 0 timing regs */
+#define _HTOTAL_DSI0		0x6b000
+#define _HSYNC_DSI0		0x6b008
+#define _VTOTAL_DSI0		0x6b00c
+#define _VSYNC_DSI0		0x6b014
+#define _VSYNCSHIFT_DSI0	0x6b028
+
+/* DSI 1 timing regs */
+#define _HTOTAL_DSI1		0x6b800
+#define _HSYNC_DSI1		0x6b808
+#define _VTOTAL_DSI1		0x6b80c
+#define _VSYNC_DSI1		0x6b814
+#define _VSYNCSHIFT_DSI1	0x6b828
+
 #define TRANSCODER_A_OFFSET 0x60000
 #define TRANSCODER_B_OFFSET 0x61000
 #define TRANSCODER_C_OFFSET 0x62000
-- 
2.11.0

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Re: [PATCH v7 14/23] drm/i915/icl: Define DSI transcoder timing registers

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines registers and bitfields used for
> programming DSI transcoder's horizontal and vertical
> timings.
>
> v2: Remove TRANS_TIMING_SHIFT definition
>
> v3 by Jani:
>   - Group macros by transcoder

Separation of DSI0 and DSI 1 specific registers are fine.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 79e633c1e9ad..c4270ca26a11 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4061,6 +4061,20 @@ enum {
>   #define _VSYNCSHIFT_B	0x61028
>   #define _PIPE_MULT_B	0x6102c
>   
> +/* DSI 0 timing regs */
> +#define _HTOTAL_DSI0		0x6b000
> +#define _HSYNC_DSI0		0x6b008
> +#define _VTOTAL_DSI0		0x6b00c
> +#define _VSYNC_DSI0		0x6b014
> +#define _VSYNCSHIFT_DSI0	0x6b028
> +
> +/* DSI 1 timing regs */
> +#define _HTOTAL_DSI1		0x6b800
> +#define _HSYNC_DSI1		0x6b808
> +#define _VTOTAL_DSI1		0x6b80c
> +#define _VSYNC_DSI1		0x6b814
> +#define _VSYNCSHIFT_DSI1	0x6b828
> +
>   #define TRANSCODER_A_OFFSET 0x60000
>   #define TRANSCODER_B_OFFSET 0x61000
>   #define TRANSCODER_C_OFFSET 0x62000

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[PATCH v7 15/23] drm/i915/icl: Configure DSI transcoder timings

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.

v2: Remove TRANS_TIMING_SHIFT usage

v3 by Jani:
 - Rebase
 - Reduce temp variable use
 - Checkpatch fix

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 118 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 87d5e6435791..f6ed57b28676 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -477,6 +477,121 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 }
 
 static void
+gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	const struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+	enum port port;
+	enum transcoder dsi_trans;
+	/* horizontal timings */
+	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
+	u16 hfront_porch, hback_porch;
+	/* vertical timings */
+	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+
+	hactive = adjusted_mode->crtc_hdisplay;
+	htotal = adjusted_mode->crtc_htotal;
+	hsync_start = adjusted_mode->crtc_hsync_start;
+	hsync_end = adjusted_mode->crtc_hsync_end;
+	hsync_size  = hsync_end - hsync_start;
+	hfront_porch = (adjusted_mode->crtc_hsync_start -
+			adjusted_mode->crtc_hdisplay);
+	hback_porch = (adjusted_mode->crtc_htotal -
+		       adjusted_mode->crtc_hsync_end);
+	vactive = adjusted_mode->crtc_vdisplay;
+	vtotal = adjusted_mode->crtc_vtotal;
+	vsync_start = adjusted_mode->crtc_vsync_start;
+	vsync_end = adjusted_mode->crtc_vsync_end;
+	vsync_shift = hsync_start - htotal / 2;
+
+	if (intel_dsi->dual_link) {
+		hactive /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			hactive += intel_dsi->pixel_overlap;
+		htotal /= 2;
+	}
+
+	/* minimum hactive as per bspec: 256 pixels */
+	if (adjusted_mode->crtc_hdisplay < 256)
+		DRM_ERROR("hactive is less then 256 pixels\n");
+
+	/* if RGB666 format, then hactive must be multiple of 4 pixels */
+	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
+		DRM_ERROR("hactive pixels are not multiple of 4\n");
+
+	/* program TRANS_HTOTAL register */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		I915_WRITE(HTOTAL(dsi_trans),
+			   (hactive - 1) | ((htotal - 1) << 16));
+	}
+
+	/* TRANS_HSYNC register to be programmed only for video mode */
+	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+		if (intel_dsi->video_mode_format ==
+		    VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+			/* BSPEC: hsync size should be atleast 16 pixels */
+			if (hsync_size < 16)
+				DRM_ERROR("hsync size < 16 pixels\n");
+		}
+
+		if (hback_porch < 16)
+			DRM_ERROR("hback porch < 16 pixels\n");
+
+		if (intel_dsi->dual_link) {
+			hsync_start /= 2;
+			hsync_end /= 2;
+		}
+
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(HSYNC(dsi_trans),
+				   (hsync_start - 1) | ((hsync_end - 1) << 16));
+		}
+	}
+
+	/* program TRANS_VTOTAL register */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		/*
+		 * FIXME: Programing this by assuming progressive mode, since
+		 * non-interlaced info from VBT is not saved inside
+		 * struct drm_display_mode.
+		 * For interlace mode: program required pixel minus 2
+		 */
+		I915_WRITE(VTOTAL(dsi_trans),
+			   (vactive - 1) | ((vtotal - 1) << 16));
+	}
+
+	if (vsync_end < vsync_start || vsync_end > vtotal)
+		DRM_ERROR("Invalid vsync_end value\n");
+
+	if (vsync_start < vactive)
+		DRM_ERROR("vsync_start less than vactive\n");
+
+	/* program TRANS_VSYNC register */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		I915_WRITE(VSYNC(dsi_trans),
+			   (vsync_start - 1) | ((vsync_end - 1) << 16));
+	}
+
+	/*
+	 * FIXME: It has to be programmed only for interlaced
+	 * modes. Put the check condition here once interlaced
+	 * info available as described above.
+	 * program TRANS_VSYNCSHIFT register
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+	}
+}
+
+static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
 {
@@ -512,4 +627,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 
 	/* step4: enable DSI port and DPHY */
 	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
+
+	/* step6c: configure transcoder timings */
+	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
 }
-- 
2.11.0

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Re: [PATCH v7 15/23] drm/i915/icl: Configure DSI transcoder timings

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> As part of DSI enable sequence, transcoder timings
> (horizontal & vertical) need to be set so that transcoder
> will generate the stream output as per those timings.
> This patch set required transcoder timings as per BSPEC.
>
> v2: Remove TRANS_TIMING_SHIFT usage
>
> v3 by Jani:
>   - Rebase
>   - Reduce temp variable use
>   - Checkpatch fix

v3 changes are fine.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 118 +++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 118 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 87d5e6435791..f6ed57b28676 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -477,6 +477,121 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>   }
>   
>   static void
> +gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> +				 const struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	const struct drm_display_mode *adjusted_mode =
> +					&pipe_config->base.adjusted_mode;
> +	enum port port;
> +	enum transcoder dsi_trans;
> +	/* horizontal timings */
> +	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
> +	u16 hfront_porch, hback_porch;
> +	/* vertical timings */
> +	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
> +
> +	hactive = adjusted_mode->crtc_hdisplay;
> +	htotal = adjusted_mode->crtc_htotal;
> +	hsync_start = adjusted_mode->crtc_hsync_start;
> +	hsync_end = adjusted_mode->crtc_hsync_end;
> +	hsync_size  = hsync_end - hsync_start;
> +	hfront_porch = (adjusted_mode->crtc_hsync_start -
> +			adjusted_mode->crtc_hdisplay);
> +	hback_porch = (adjusted_mode->crtc_htotal -
> +		       adjusted_mode->crtc_hsync_end);
> +	vactive = adjusted_mode->crtc_vdisplay;
> +	vtotal = adjusted_mode->crtc_vtotal;
> +	vsync_start = adjusted_mode->crtc_vsync_start;
> +	vsync_end = adjusted_mode->crtc_vsync_end;
> +	vsync_shift = hsync_start - htotal / 2;
> +
> +	if (intel_dsi->dual_link) {
> +		hactive /= 2;
> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
> +			hactive += intel_dsi->pixel_overlap;
> +		htotal /= 2;
> +	}
> +
> +	/* minimum hactive as per bspec: 256 pixels */
> +	if (adjusted_mode->crtc_hdisplay < 256)
> +		DRM_ERROR("hactive is less then 256 pixels\n");
> +
> +	/* if RGB666 format, then hactive must be multiple of 4 pixels */
> +	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
> +		DRM_ERROR("hactive pixels are not multiple of 4\n");
> +
> +	/* program TRANS_HTOTAL register */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		I915_WRITE(HTOTAL(dsi_trans),
> +			   (hactive - 1) | ((htotal - 1) << 16));
> +	}
> +
> +	/* TRANS_HSYNC register to be programmed only for video mode */
> +	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
> +		if (intel_dsi->video_mode_format ==
> +		    VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
> +			/* BSPEC: hsync size should be atleast 16 pixels */
> +			if (hsync_size < 16)
> +				DRM_ERROR("hsync size < 16 pixels\n");
> +		}
> +
> +		if (hback_porch < 16)
> +			DRM_ERROR("hback porch < 16 pixels\n");
> +
> +		if (intel_dsi->dual_link) {
> +			hsync_start /= 2;
> +			hsync_end /= 2;
> +		}
> +
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			dsi_trans = dsi_port_to_transcoder(port);
> +			I915_WRITE(HSYNC(dsi_trans),
> +				   (hsync_start - 1) | ((hsync_end - 1) << 16));
> +		}
> +	}
> +
> +	/* program TRANS_VTOTAL register */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		/*
> +		 * FIXME: Programing this by assuming progressive mode, since
> +		 * non-interlaced info from VBT is not saved inside
> +		 * struct drm_display_mode.
> +		 * For interlace mode: program required pixel minus 2
> +		 */
> +		I915_WRITE(VTOTAL(dsi_trans),
> +			   (vactive - 1) | ((vtotal - 1) << 16));
> +	}
> +
> +	if (vsync_end < vsync_start || vsync_end > vtotal)
> +		DRM_ERROR("Invalid vsync_end value\n");
> +
> +	if (vsync_start < vactive)
> +		DRM_ERROR("vsync_start less than vactive\n");
> +
> +	/* program TRANS_VSYNC register */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		I915_WRITE(VSYNC(dsi_trans),
> +			   (vsync_start - 1) | ((vsync_end - 1) << 16));
> +	}
> +
> +	/*
> +	 * FIXME: It has to be programmed only for interlaced
> +	 * modes. Put the check condition here once interlaced
> +	 * info available as described above.
> +	 * program TRANS_VSYNCSHIFT register
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
> +	}
> +}
> +
> +static void
>   gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *pipe_config)
>   {
> @@ -512,4 +627,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
>   
>   	/* step4: enable DSI port and DPHY */
>   	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
> +
> +	/* step6c: configure transcoder timings */
> +	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>   }

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[PATCH v7 16/23] drm/i915/icl: Define TRANS_CONF register for DSI

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch defines TRANS_CONF registers for DSI ports
0 and 1. Bitfields of these registers used for enabling
and reading the current state of transcoder.

v2: Add blank line before comment

v3 by Jani:
 - Move DSI specific .pipe_offsets to GEN11_FEATURES
 - Macro placement and comment juggling

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b86b735a8634..44e745921ac1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = {
 
 #define GEN11_FEATURES \
 	GEN10_FEATURES, \
+	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
+			  PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
+			  PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
 	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
 			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
 			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4270ca26a11..839e681bd3a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5652,6 +5652,10 @@ enum {
  */
 #define PIPE_EDP_OFFSET	0x7f000
 
+/* ICL DSI 0 and 1 */
+#define PIPE_DSI0_OFFSET	0x7b000
+#define PIPE_DSI1_OFFSET	0x7b800
+
 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
 	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
 	dev_priv->info.display_mmio_offset)
@@ -6240,6 +6244,10 @@ enum {
 #define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
 #define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
 
+/* ICL DSI 0 and 1 */
+#define _PIPEDSI0CONF		0x7b008
+#define _PIPEDSI1CONF		0x7b808
+
 /* Sprite A control */
 #define _DVSACNTR		0x72180
 #define   DVS_ENABLE		(1 << 31)
-- 
2.11.0

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Re: [PATCH v7 16/23] drm/i915/icl: Define TRANS_CONF register for DSI

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines TRANS_CONF registers for DSI ports
> 0 and 1. Bitfields of these registers used for enabling
> and reading the current state of transcoder.
>
> v2: Add blank line before comment
>
> v3 by Jani:
>   - Move DSI specific .pipe_offsets to GEN11_FEATURES
>   - Macro placement and comment juggling

Changes looks ok.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c | 3 +++
>   drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b86b735a8634..44e745921ac1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = {
>   
>   #define GEN11_FEATURES \
>   	GEN10_FEATURES, \
> +	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> +			  PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
> +			  PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
>   	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
>   			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
>   			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c4270ca26a11..839e681bd3a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5652,6 +5652,10 @@ enum {
>    */
>   #define PIPE_EDP_OFFSET	0x7f000
>   
> +/* ICL DSI 0 and 1 */
> +#define PIPE_DSI0_OFFSET	0x7b000
> +#define PIPE_DSI1_OFFSET	0x7b800
> +
>   #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
>   	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
>   	dev_priv->info.display_mmio_offset)
> @@ -6240,6 +6244,10 @@ enum {
>   #define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
>   #define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
>   
> +/* ICL DSI 0 and 1 */
> +#define _PIPEDSI0CONF		0x7b008
> +#define _PIPEDSI1CONF		0x7b808
> +
>   /* Sprite A control */
>   #define _DVSACNTR		0x72180
>   #define   DVS_ENABLE		(1 << 31)

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[PATCH v7 17/23] drm/i915/icl: Enable DSI transcoders

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch enables DSI transcoders by writing to
TRANS_CONF registers and wait for its state to be enabled.

v2 by Jani:
 - Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f6ed57b28676..216a1753d246 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -591,6 +591,28 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 }
 
+static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	enum transcoder dsi_trans;
+	u32 tmp;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(PIPECONF(dsi_trans));
+		tmp |= PIPECONF_ENABLE;
+		I915_WRITE(PIPECONF(dsi_trans), tmp);
+
+		/* wait for transcoder to be enabled */
+		if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+					    I965_PIPECONF_ACTIVE,
+					    I965_PIPECONF_ACTIVE, 10))
+			DRM_ERROR("DSI transcoder not enabled\n");
+	}
+}
+
 static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
@@ -630,4 +652,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 
 	/* step6c: configure transcoder timings */
 	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
+
+	/* step6d: enable dsi transcoder */
+	gen11_dsi_enable_transcoder(encoder);
 }
-- 
2.11.0

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Re: [PATCH v7 17/23] drm/i915/icl: Enable DSI transcoders

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch enables DSI transcoders by writing to
> TRANS_CONF registers and wait for its state to be enabled.
>
> v2 by Jani:
>   - Rebase

Patch *17-23* changes like rebase, alignment, comments style changes looks
good to me.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index f6ed57b28676..216a1753d246 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -591,6 +591,28 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>   	}
>   }
>   
> +static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	enum transcoder dsi_trans;
> +	u32 tmp;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		tmp = I915_READ(PIPECONF(dsi_trans));
> +		tmp |= PIPECONF_ENABLE;
> +		I915_WRITE(PIPECONF(dsi_trans), tmp);
> +
> +		/* wait for transcoder to be enabled */
> +		if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
> +					    I965_PIPECONF_ACTIVE,
> +					    I965_PIPECONF_ACTIVE, 10))
> +			DRM_ERROR("DSI transcoder not enabled\n");
> +	}
> +}
> +
>   static void
>   gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *pipe_config)
> @@ -630,4 +652,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
>   
>   	/* step6c: configure transcoder timings */
>   	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> +
> +	/* step6d: enable dsi transcoder */
> +	gen11_dsi_enable_transcoder(encoder);
>   }

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[PATCH v7 18/23] drm/i915/icl: Define DSI panel programming registers

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch defines DSI_CMD_RXCTL, DSI_CMD_TXCTL registers,
bitfields, masks and macros used for configuring DSI panel.

v2: Define remaining bitfields

v3 by Jani:
 - Alignment fix

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 839e681bd3a4..fe6b42037ded 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10463,6 +10463,44 @@ enum skl_power_gate {
 #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
 #define  EOTP_DISABLED			(1 << 0)
 
+#define _DSI_CMD_RXCTL_0		0x6b0d4
+#define _DSI_CMD_RXCTL_1		0x6b8d4
+#define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
+						  _DSI_CMD_RXCTL_0,\
+						  _DSI_CMD_RXCTL_1)
+#define  READ_UNLOADS_DW		(1 << 16)
+#define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
+#define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
+#define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
+#define  RECEIVED_RESET_TRIGGER		(1 << 12)
+#define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
+#define  RECEIVED_CRC_WAS_LOST		(1 << 10)
+#define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
+#define  NUMBER_RX_PLOAD_DW_SHIFT	0
+
+#define _DSI_CMD_TXCTL_0		0x6b0d0
+#define _DSI_CMD_TXCTL_1		0x6b8d0
+#define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
+						  _DSI_CMD_TXCTL_0,\
+						  _DSI_CMD_TXCTL_1)
+#define  KEEP_LINK_IN_HS		(1 << 24)
+#define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
+#define  FREE_HEADER_CREDIT_SHIFT	0x8
+#define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
+#define  FREE_PLOAD_CREDIT_SHIFT	0
+#define  MAX_HEADER_CREDIT		0x10
+#define  MAX_PLOAD_CREDIT		0x40
+
+#define _DSI_LP_MSG_0			0x6b0d8
+#define _DSI_LP_MSG_1			0x6b8d8
+#define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
+						  _DSI_LP_MSG_0,\
+						  _DSI_LP_MSG_1)
+#define  LPTX_IN_PROGRESS		(1 << 17)
+#define  LINK_IN_ULPS			(1 << 16)
+#define  LINK_ULPS_TYPE_LP11		(1 << 8)
+#define  LINK_ENTER_ULPS		(1 << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.11.0

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Re: [PATCH v7 18/23] drm/i915/icl: Define DSI panel programming registers

[Jani Nikula]

On Mon, 15 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines DSI_CMD_RXCTL, DSI_CMD_TXCTL registers,
> bitfields, masks and macros used for configuring DSI panel.
>
> v2: Define remaining bitfields
>
> v3 by Jani:
>  - Alignment fix
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Pushed up to and including this patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 839e681bd3a4..fe6b42037ded 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10463,6 +10463,44 @@ enum skl_power_gate {
>  #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
>  #define  EOTP_DISABLED			(1 << 0)
>  
> +#define _DSI_CMD_RXCTL_0		0x6b0d4
> +#define _DSI_CMD_RXCTL_1		0x6b8d4
> +#define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
> +						  _DSI_CMD_RXCTL_0,\
> +						  _DSI_CMD_RXCTL_1)
> +#define  READ_UNLOADS_DW		(1 << 16)
> +#define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
> +#define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
> +#define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
> +#define  RECEIVED_RESET_TRIGGER		(1 << 12)
> +#define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
> +#define  RECEIVED_CRC_WAS_LOST		(1 << 10)
> +#define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
> +#define  NUMBER_RX_PLOAD_DW_SHIFT	0
> +
> +#define _DSI_CMD_TXCTL_0		0x6b0d0
> +#define _DSI_CMD_TXCTL_1		0x6b8d0
> +#define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
> +						  _DSI_CMD_TXCTL_0,\
> +						  _DSI_CMD_TXCTL_1)
> +#define  KEEP_LINK_IN_HS		(1 << 24)
> +#define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
> +#define  FREE_HEADER_CREDIT_SHIFT	0x8
> +#define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
> +#define  FREE_PLOAD_CREDIT_SHIFT	0
> +#define  MAX_HEADER_CREDIT		0x10
> +#define  MAX_PLOAD_CREDIT		0x40
> +
> +#define _DSI_LP_MSG_0			0x6b0d8
> +#define _DSI_LP_MSG_1			0x6b8d8
> +#define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
> +						  _DSI_LP_MSG_0,\
> +						  _DSI_LP_MSG_1)
> +#define  LPTX_IN_PROGRESS		(1 << 17)
> +#define  LINK_IN_ULPS			(1 << 16)
> +#define  LINK_ULPS_TYPE_LP11		(1 << 8)
> +#define  LINK_ENTER_ULPS		(1 << 0)
> +
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

-- 
Jani Nikula, Intel Open Source Graphics Center
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[PATCH v7 19/23] drm/i915/icl: Set max return packet size for DSI panel

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

---

FIXME: Looks like this is storing sw state in registers.
---
 drivers/gpu/drm/i915/icl_dsi.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 216a1753d246..5ede055b263e 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -25,6 +25,7 @@
  *   Jani Nikula <jani.nikula@intel.com>
  */
 
+#include <drm/drm_mipi_dsi.h>
 #include "intel_dsi.h"
 
 static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -636,6 +637,30 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	gen11_dsi_configure_transcoder(encoder, pipe_config);
 }
 
+static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct mipi_dsi_device *dsi;
+	enum port port;
+	enum transcoder dsi_trans;
+	u32 tmp;
+	int ret;
+
+	/* set maximum return packet size */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
+		tmp &= NUMBER_RX_PLOAD_DW_MASK;
+		/* multiply "Number Rx Payload DW" by 4 to get max value */
+		tmp = tmp * 4;
+		dsi = intel_dsi->dsi_hosts[port]->device;
+		ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
+		if (ret < 0)
+			DRM_ERROR("error setting max return pkt size%d\n", tmp);
+	}
+}
+
 static void __attribute__((unused))
 gen11_dsi_pre_enable(struct intel_encoder *encoder,
 		     const struct intel_crtc_state *pipe_config,
@@ -650,6 +675,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 	/* step4: enable DSI port and DPHY */
 	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
 
+	/* step5: program and powerup panel */
+	gen11_dsi_powerup_panel(encoder);
+
 	/* step6c: configure transcoder timings */
 	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
 
-- 
2.11.0

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[PATCH v7 20/23] drm/i915/icl: Power on DSI panel

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch execute poweron, deassert reset, display on
VBT sequences and send TURN_ON DSI command to panel for
powering it up.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 5ede055b263e..0393fed98a6f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -659,6 +659,13 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 		if (ret < 0)
 			DRM_ERROR("error setting max return pkt size%d\n", tmp);
 	}
+
+	/* panel power on related mipi dsi vbt sequences */
+	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
+	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
+	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
+	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 }
 
 static void __attribute__((unused))
-- 
2.11.0

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[PATCH v7 21/23] drm/i915/icl: Wait for header/payload credits release

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0393fed98a6f..5fe024dfbdb0 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -28,6 +28,30 @@
 #include <drm/drm_mipi_dsi.h>
 #include "intel_dsi.h"
 
+static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(
+						struct intel_dsi *intel_dsi,
+						enum transcoder dsi_trans)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+	if (wait_for_us(((I915_READ(DSI_CMD_TXCTL(dsi_trans)) &
+			  FREE_HEADER_CREDIT_MASK) >> FREE_HEADER_CREDIT_SHIFT)
+			  == MAX_HEADER_CREDIT, 100))
+		DRM_ERROR("DSI header credits not released\n");
+}
+
+static void __attribute__((unused)) wait_for_dsi_payload_credit_release(
+						struct intel_dsi *intel_dsi,
+						enum transcoder dsi_trans)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+	if (wait_for_us((I915_READ(DSI_CMD_TXCTL(dsi_trans)) &
+			FREE_PLOAD_CREDIT_MASK) == MAX_PLOAD_CREDIT,
+			100))
+		DRM_ERROR("DSI payload credits not released\n");
+}
+
 static enum transcoder dsi_port_to_transcoder(enum port port)
 {
 	if (port == PORT_A)
-- 
2.11.0

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[PATCH v7 22/23] drm/i915/icl: Ensure all cmd/data disptached to panel

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

As per BSPEC, driver needs to ensure that all of commands/data
has been dispatched to panel before the transcoder is enabled.
This patch implement those steps i.e. sending NOP DCS command,
wait for header/payload credit to be released etc.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 53 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 48 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 5fe024dfbdb0..90188ba8a4dc 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -28,9 +28,8 @@
 #include <drm/drm_mipi_dsi.h>
 #include "intel_dsi.h"
 
-static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(
-						struct intel_dsi *intel_dsi,
-						enum transcoder dsi_trans)
+static void wait_for_dsi_hdr_credit_release(struct intel_dsi *intel_dsi,
+					    enum transcoder dsi_trans)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 
@@ -40,8 +39,7 @@ static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(
 		DRM_ERROR("DSI header credits not released\n");
 }
 
-static void __attribute__((unused)) wait_for_dsi_payload_credit_release(
-						struct intel_dsi *intel_dsi,
+static void wait_for_dsi_payload_credit_release(struct intel_dsi *intel_dsi,
 						enum transcoder dsi_trans)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
@@ -60,6 +58,48 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
 		return TRANSCODER_DSI_1;
 }
 
+static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct mipi_dsi_device *dsi;
+	enum port port;
+	enum transcoder dsi_trans;
+	int ret;
+
+	/* wait for header/payload credits to be released */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		wait_for_dsi_hdr_credit_release(intel_dsi, dsi_trans);
+		wait_for_dsi_payload_credit_release(intel_dsi, dsi_trans);
+	}
+
+	/* send nop DCS command */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi = intel_dsi->dsi_hosts[port]->device;
+		dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+		dsi->channel = 0;
+		ret = mipi_dsi_dcs_nop(dsi);
+		if (ret < 0)
+			DRM_ERROR("error sending DCS NOP command\n");
+	}
+
+	/* wait for header credits to be released */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		wait_for_dsi_hdr_credit_release(intel_dsi, dsi_trans);
+	}
+
+	/* wait for LP TX in progress bit to be cleared */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
+				  LPTX_IN_PROGRESS),
+				  20))
+			DRM_ERROR("LPTX bit not cleared\n");
+	}
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -690,6 +730,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
+
+	/* ensure all panel commands dispatched before enabling transcoder */
+	wait_for_cmds_dispatched_to_panel(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.11.0

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[PATCH v7 23/23] drm/i915/icl: Turn ON panel backlight

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch enables backlight of DSI panel by using VBT
BACKLIGHT_ON sequence and panel specific functions.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 90188ba8a4dc..7ea6741e37ac 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -740,6 +740,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 		     const struct intel_crtc_state *pipe_config,
 		     const struct drm_connector_state *conn_state)
 {
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
 	/* step2: enable IO power */
 	gen11_dsi_enable_io_power(encoder);
 
@@ -757,4 +759,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 
 	/* step6d: enable dsi transcoder */
 	gen11_dsi_enable_transcoder(encoder);
+
+	/* step7: enable backlight */
+	intel_panel_enable_backlight(pipe_config, conn_state);
+	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 }
-- 
2.11.0

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✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling
URL   : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b12abf6e31c4 drm/i915: make encoder enable and disable hooks optional
1a879a6d5120 drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#29: 
new file mode 100644

-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:552:
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);

total: 0 errors, 2 warnings, 0 checks, 118 lines checked
b14852354e52 drm/i915/dsi: abstract dphy parameter init
-:129: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#129: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:691:
+			pixel_format_from_register_bits(

-:155: WARNING:BRACES: braces {} are not necessary for single statement blocks
#155: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:717:
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
+		}

-:156: WARNING:LONG_LINE: line over 100 characters
#156: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:718:
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);

-:164: CHECK:BRACES: braces {} should be used on all arms of this statement
#164: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:726:
+	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
[...]
+	} else
[...]

-:173: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#173: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:735:
+			burst_mode_ratio = DIV_ROUND_UP(

-:182: CHECK:BRACES: Unbalanced braces around else statement
#182: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:744:
+	} else

total: 0 errors, 2 warnings, 4 checks, 169 lines checked
f747b1606322 drm/i915/dsi: abstract intel_dsi_tlpx_ns()
f5d8752673e3 drm/i915/icl: Make common DSI functions available
1766764bfdc9 drm/i915/icl: Program DSI clock and data lane timing params
51bb6f5afbd6 drm/i915/icl: Program TA_TIMING_PARAM registers
0e2b629b050f drm/i915/icl: Get DSI transcoder for a given port
f214bf74072b drm/i915/icl: Add macros for MMIO of DSI transcoder registers
5dcfc9bcf556 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
8fedd977c309 drm/i915/icl: Configure DSI transcoders
-:146: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#146: FILE: drivers/gpu/drm/i915/intel_dsi.h:85:
+	bool bgr_enabled;

total: 0 errors, 0 warnings, 1 checks, 121 lines checked
fa60d3c6232b drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
c4b1dbebffe2 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
16b3a933fd57 drm/i915/icl: Define DSI transcoder timing registers
f40776f438c5 drm/i915/icl: Configure DSI transcoder timings
2798285cb709 drm/i915/icl: Define TRANS_CONF register for DSI
45434712c8ed drm/i915/icl: Enable DSI transcoders
b4e25fc83b04 drm/i915/icl: Define DSI panel programming registers
8fbeffd78efd drm/i915/icl: Set max return packet size for DSI panel
b4f147d6e59a drm/i915/icl: Power on DSI panel
2ded53515fac drm/i915/icl: Wait for header/payload credits release
-:22: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#22: FILE: drivers/gpu/drm/i915/icl_dsi.c:31:
+static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(

-:34: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#34: FILE: drivers/gpu/drm/i915/icl_dsi.c:43:
+static void __attribute__((unused)) wait_for_dsi_payload_credit_release(

total: 0 errors, 0 warnings, 2 checks, 30 lines checked
f24121c2b8aa drm/i915/icl: Ensure all cmd/data disptached to panel
40cd071d495a drm/i915/icl: Turn ON panel backlight

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✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling
URL   : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: make encoder enable and disable hooks optional
Okay!

Commit: drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

Commit: drm/i915/dsi: abstract dphy parameter init
Okay!

Commit: drm/i915/dsi: abstract intel_dsi_tlpx_ns()
Okay!

Commit: drm/i915/icl: Make common DSI functions available
Okay!

Commit: drm/i915/icl: Program DSI clock and data lane timing params
+drivers/gpu/drm/i915/intel_dsi_vbt.c:534:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:534:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:535:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:535:26: warning: expression using sizeof(void)

Commit: drm/i915/icl: Program TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Get DSI transcoder for a given port
Okay!

Commit: drm/i915/icl: Add macros for MMIO of DSI transcoder registers
Okay!

Commit: drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
Okay!

Commit: drm/i915/icl: Configure DSI transcoders
Okay!

Commit: drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
Okay!

Commit: drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
Okay!

Commit: drm/i915/icl: Define DSI transcoder timing registers
Okay!

Commit: drm/i915/icl: Configure DSI transcoder timings
Okay!

Commit: drm/i915/icl: Define TRANS_CONF register for DSI
Okay!

Commit: drm/i915/icl: Enable DSI transcoders
Okay!

Commit: drm/i915/icl: Define DSI panel programming registers
Okay!

Commit: drm/i915/icl: Set max return packet size for DSI panel
Okay!

Commit: drm/i915/icl: Power on DSI panel
Okay!

Commit: drm/i915/icl: Wait for header/payload credits release
Okay!

Commit: drm/i915/icl: Ensure all cmd/data disptached to panel
Okay!

Commit: drm/i915/icl: Turn ON panel backlight
Okay!

_______________________________________________
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✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling
URL   : https://patchwork.freedesktop.org/series/51011/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4981 -> Patchwork_10459 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10459 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10459, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10459:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_busy@basic-flip-a:
      fi-icl-u2:          PASS -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_10459 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#105998)

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
      fi-ilk-650:         PASS -> DMESG-WARN (fdo#106387) +1

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      fi-icl-u:           INCOMPLETE (fdo#107713) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@pm_rpm@module-reload:
      {fi-apl-guc}:       DMESG-WARN (fdo#106685) -> PASS
      fi-skl-6600u:       INCOMPLETE (fdo#107807) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
  fdo#106685 https://bugs.freedesktop.org/show_bug.cgi?id=106685
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807


== Participating hosts (54 -> 48) ==

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_4981 -> Patchwork_10459

  CI_DRM_4981: 79887268bfe4128788d7cfcf38b62308346fd7f1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4677: 68ff28a022dbaa26a20c8a3c0212011a006614b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10459: 40cd071d495aebb20871cb992c8b7163d6bd89f8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

40cd071d495a drm/i915/icl: Turn ON panel backlight
f24121c2b8aa drm/i915/icl: Ensure all cmd/data disptached to panel
2ded53515fac drm/i915/icl: Wait for header/payload credits release
b4f147d6e59a drm/i915/icl: Power on DSI panel
8fbeffd78efd drm/i915/icl: Set max return packet size for DSI panel
b4e25fc83b04 drm/i915/icl: Define DSI panel programming registers
45434712c8ed drm/i915/icl: Enable DSI transcoders
2798285cb709 drm/i915/icl: Define TRANS_CONF register for DSI
f40776f438c5 drm/i915/icl: Configure DSI transcoder timings
16b3a933fd57 drm/i915/icl: Define DSI transcoder timing registers
c4b1dbebffe2 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
fa60d3c6232b drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
8fedd977c309 drm/i915/icl: Configure DSI transcoders
5dcfc9bcf556 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
f214bf74072b drm/i915/icl: Add macros for MMIO of DSI transcoder registers
0e2b629b050f drm/i915/icl: Get DSI transcoder for a given port
51bb6f5afbd6 drm/i915/icl: Program TA_TIMING_PARAM registers
1766764bfdc9 drm/i915/icl: Program DSI clock and data lane timing params
f5d8752673e3 drm/i915/icl: Make common DSI functions available
f747b1606322 drm/i915/dsi: abstract intel_dsi_tlpx_ns()
b14852354e52 drm/i915/dsi: abstract dphy parameter init
1a879a6d5120 drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
b12abf6e31c4 drm/i915: make encoder enable and disable hooks optional

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10459/issues.html
_______________________________________________
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Re: [PATCH v7 00/23] drm/i915/icl: dsi enabling

[Jani Nikula]

On Mon, 15 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> The v7 is a bit misleading, but it's essentially the next version of
> [1], embedding my review into the commits directly. This is the first
> batch from me, and there's more to come.

The full series also at icl-dsi-2018-10-16 branch of
https://cgit.freedesktop.org/~jani/drm/

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
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✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c25368a8ec1e drm/i915: make encoder enable and disable hooks optional
-:44: WARNING:LONG_LINE: line over 100 characters
#44: FILE: drivers/gpu/drm/i915/intel_display.c:15448:
+				encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);

total: 0 errors, 1 warnings, 0 checks, 61 lines checked
f9a6a6ec351f drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

-:114: WARNING:LONG_LINE: line over 100 characters
#114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:552:
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);

total: 0 errors, 2 warnings, 0 checks, 118 lines checked
efa9b026e207 drm/i915/dsi: abstract dphy parameter init
-:130: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#130: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:691:
+			pixel_format_from_register_bits(

-:156: WARNING:BRACES: braces {} are not necessary for single statement blocks
#156: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:717:
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
+		}

-:157: WARNING:LONG_LINE: line over 100 characters
#157: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:718:
+			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);

-:165: CHECK:BRACES: braces {} should be used on all arms of this statement
#165: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:726:
+	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
[...]
+	} else
[...]

-:174: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#174: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:735:
+			burst_mode_ratio = DIV_ROUND_UP(

-:183: CHECK:BRACES: Unbalanced braces around else statement
#183: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:744:
+	} else

total: 0 errors, 2 warnings, 4 checks, 169 lines checked
0b6b3d7d10f9 drm/i915/dsi: abstract intel_dsi_tlpx_ns()
4ea7560e8bf0 drm/i915/icl: Make common DSI functions available
8dd4accf0f08 drm/i915/icl: Program DSI clock and data lane timing params
3887d2f3fc66 drm/i915/icl: Program TA_TIMING_PARAM registers
d45e6957f8bc drm/i915/icl: Get DSI transcoder for a given port
82e9c3ba9891 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
c6be44e9b750 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
d9fddc1fdb98 drm/i915/icl: Configure DSI transcoders
-:146: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#146: FILE: drivers/gpu/drm/i915/intel_dsi.h:85:
+	bool bgr_enabled;

total: 0 errors, 0 warnings, 1 checks, 121 lines checked
3b0bc52936dc drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
3a6e7dbce100 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
c13805c69a43 drm/i915/icl: Define DSI transcoder timing registers
27b32fd273e3 drm/i915/icl: Configure DSI transcoder timings
d52459f4c75c drm/i915/icl: Define TRANS_CONF register for DSI
952873ccf0b2 drm/i915/icl: Enable DSI transcoders
fd4c6e67e010 drm/i915/icl: Define DSI panel programming registers
cdece01f26bf drm/i915/icl: Set max return packet size for DSI panel
894c9626886b drm/i915/icl: Power on DSI panel
b2d70882145b drm/i915/icl: Wait for header/payload credits release
-:22: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#22: FILE: drivers/gpu/drm/i915/icl_dsi.c:31:
+static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(

-:34: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#34: FILE: drivers/gpu/drm/i915/icl_dsi.c:43:
+static void __attribute__((unused)) wait_for_dsi_payload_credit_release(

total: 0 errors, 0 warnings, 2 checks, 30 lines checked
07124f12764f drm/i915/icl: Ensure all cmd/data disptached to panel
8a33c1840e00 drm/i915/icl: Turn ON panel backlight

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✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: make encoder enable and disable hooks optional
Okay!

Commit: drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

Commit: drm/i915/dsi: abstract dphy parameter init
Okay!

Commit: drm/i915/dsi: abstract intel_dsi_tlpx_ns()
Okay!

Commit: drm/i915/icl: Make common DSI functions available
Okay!

Commit: drm/i915/icl: Program DSI clock and data lane timing params
+drivers/gpu/drm/i915/intel_dsi_vbt.c:534:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:534:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:535:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:535:26: warning: expression using sizeof(void)

Commit: drm/i915/icl: Program TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Get DSI transcoder for a given port
Okay!

Commit: drm/i915/icl: Add macros for MMIO of DSI transcoder registers
Okay!

Commit: drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
Okay!

Commit: drm/i915/icl: Configure DSI transcoders
Okay!

Commit: drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
Okay!

Commit: drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
Okay!

Commit: drm/i915/icl: Define DSI transcoder timing registers
Okay!

Commit: drm/i915/icl: Configure DSI transcoder timings
Okay!

Commit: drm/i915/icl: Define TRANS_CONF register for DSI
Okay!

Commit: drm/i915/icl: Enable DSI transcoders
Okay!

Commit: drm/i915/icl: Define DSI panel programming registers
Okay!

Commit: drm/i915/icl: Set max return packet size for DSI panel
Okay!

Commit: drm/i915/icl: Power on DSI panel
Okay!

Commit: drm/i915/icl: Wait for header/payload credits release
Okay!

Commit: drm/i915/icl: Ensure all cmd/data disptached to panel
Okay!

Commit: drm/i915/icl: Turn ON panel backlight
Okay!

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✓ Fi.CI.BAT: success for drm/i915/icl: dsi enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/51011/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4987 -> Patchwork_10473 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10473 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_basic@cs-compute:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#108094)

    igt@amdgpu/amd_cs_nop@fork-gfx0:
      fi-kbl-8809g:       NOTRUN -> DMESG-WARN (fdo#107762)

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#107341)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       PASS -> DMESG-WARN (fdo#107139, fdo#105128)

    igt@kms_frontbuffer_tracking@basic:
      fi-icl-u2:          PASS -> FAIL (fdo#103167)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload-inject:
      fi-glk-j4005:       DMESG-WARN (fdo#106725, fdo#106248) -> PASS

    igt@kms_flip@basic-flip-vs-dpms:
      fi-glk-j4005:       DMESG-WARN (fdo#106000) -> PASS

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
      fi-skl-6700k2:      FAIL (fdo#103191, fdo#107362) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-cfl-8109u:       INCOMPLETE (fdo#108126, fdo#106070) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
  fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107762 https://bugs.freedesktop.org/show_bug.cgi?id=107762
  fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094
  fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126


== Participating hosts (49 -> 44) ==

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_4987 -> Patchwork_10473

  CI_DRM_4987: 6f1fe37189c04cb62e73e7a9e075f012c7fc45ff @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4680: 27fa97d16294af9c9c42fd81b030a73e4aa2e7c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10473: 8a33c1840e0059c873e427a4b88ae30b09360d3c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8a33c1840e00 drm/i915/icl: Turn ON panel backlight
07124f12764f drm/i915/icl: Ensure all cmd/data disptached to panel
b2d70882145b drm/i915/icl: Wait for header/payload credits release
894c9626886b drm/i915/icl: Power on DSI panel
cdece01f26bf drm/i915/icl: Set max return packet size for DSI panel
fd4c6e67e010 drm/i915/icl: Define DSI panel programming registers
952873ccf0b2 drm/i915/icl: Enable DSI transcoders
d52459f4c75c drm/i915/icl: Define TRANS_CONF register for DSI
27b32fd273e3 drm/i915/icl: Configure DSI transcoder timings
c13805c69a43 drm/i915/icl: Define DSI transcoder timing registers
3a6e7dbce100 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
3b0bc52936dc drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
d9fddc1fdb98 drm/i915/icl: Configure DSI transcoders
c6be44e9b750 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
82e9c3ba9891 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
d45e6957f8bc drm/i915/icl: Get DSI transcoder for a given port
3887d2f3fc66 drm/i915/icl: Program TA_TIMING_PARAM registers
8dd4accf0f08 drm/i915/icl: Program DSI clock and data lane timing params
4ea7560e8bf0 drm/i915/icl: Make common DSI functions available
0b6b3d7d10f9 drm/i915/dsi: abstract intel_dsi_tlpx_ns()
efa9b026e207 drm/i915/dsi: abstract dphy parameter init
f9a6a6ec351f drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
c25368a8ec1e drm/i915: make encoder enable and disable hooks optional

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10473/issues.html
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✗ Fi.CI.IGT: failure for drm/i915/icl: dsi enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/51011/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4987_full -> Patchwork_10473_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10473_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10473_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10473_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_color@pipe-a-ctm-green-to-red:
      shard-skl:          PASS -> FAIL

    
    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-kbl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10473_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries_display_off:
      shard-skl:          PASS -> INCOMPLETE (fdo#104108)

    igt@kms_busy@extended-modeset-hang-newfb-render-a:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
      shard-hsw:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_busy@extended-pageflip-hang-newfb-render-a:
      shard-glk:          NOTRUN -> DMESG-WARN (fdo#107956) +3

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
      shard-snb:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
      shard-kbl:          PASS -> DMESG-WARN (fdo#107956)

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          NOTRUN -> FAIL (fdo#106509, fdo#105454)

    igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
      shard-skl:          PASS -> FAIL (fdo#103184)

    igt@kms_fbcon_fbt@fbc-suspend:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927) +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt:
      shard-glk:          NOTRUN -> FAIL (fdo#103167) +1

    igt@kms_plane@pixel-format-pipe-a-planes:
      shard-glk:          NOTRUN -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
      shard-glk:          NOTRUN -> FAIL (fdo#108145) +2

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-apl:          PASS -> FAIL (fdo#103166)

    igt@pm_rpm@debugfs-read:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807)

    
    ==== Possible fixes ====

    igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge:
      shard-skl:          FAIL (fdo#104671) -> PASS +1

    igt@kms_cursor_crc@cursor-128x128-suspend:
      shard-apl:          FAIL (fdo#103191, fdo#103232) -> PASS

    igt@kms_cursor_crc@cursor-size-change:
      shard-glk:          FAIL (fdo#103232) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
      shard-glk:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
      shard-skl:          FAIL (fdo#105682) -> PASS

    igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
      shard-skl:          FAIL (fdo#103167) -> PASS +2

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      shard-apl:          DMESG-WARN (fdo#105602, fdo#103558) -> PASS +1

    igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
      shard-apl:          FAIL (fdo#103166) -> PASS

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4987 -> Patchwork_10473

  CI_DRM_4987: 6f1fe37189c04cb62e73e7a9e075f012c7fc45ff @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4680: 27fa97d16294af9c9c42fd81b030a73e4aa2e7c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10473: 8a33c1840e0059c873e427a4b88ae30b09360d3c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10473/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915/icl: dsi enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/51011/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4995 -> Patchwork_10486 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10486 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      fi-icl-u:           PASS -> INCOMPLETE (fdo#108315)

    igt@kms_frontbuffer_tracking@basic:
      fi-icl-u2:          PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      fi-kbl-7560u:       INCOMPLETE (fdo#108044) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044
  fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315


== Participating hosts (46 -> 42) ==

  Additional (1): fi-pnv-d510 
  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 


== Build changes ==

    * Linux: CI_DRM_4995 -> Patchwork_10486

  CI_DRM_4995: 54f2281117133d77122fe452af3ea0bd5b6161aa @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4683: 7766b1e2348b32cc8ed58a972c6fd53b20279549 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10486: 77756b23dbf159cd95e7379afb52a211d31e41bb @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

77756b23dbf1 drm/i915/icl: Turn ON panel backlight
1c32080b780f drm/i915/icl: Ensure all cmd/data disptached to panel
e127dd920d4c drm/i915/icl: Wait for header/payload credits release
548a139f5f39 drm/i915/icl: Power on DSI panel
de595aced252 drm/i915/icl: Set max return packet size for DSI panel
ceccb56049de drm/i915/icl: Define DSI panel programming registers
84bfd208073a drm/i915/icl: Enable DSI transcoders
db56c3a6111b drm/i915/icl: Define TRANS_CONF register for DSI
71a178875a37 drm/i915/icl: Configure DSI transcoder timings
a3128e344e49 drm/i915/icl: Define DSI transcoder timing registers
563acc8957df drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
4effa0a65f78 drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
cc0a0db6d765 drm/i915/icl: Configure DSI transcoders
190f8e155498 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
aaddb12846e7 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
3e59c4c21a59 drm/i915/icl: Get DSI transcoder for a given port
914a8a8a1c8f drm/i915/icl: Program TA_TIMING_PARAM registers
f8fa35845dbc drm/i915/icl: Program DSI clock and data lane timing params
64d22dff235d drm/i915/icl: Make common DSI functions available
eb89224c27f6 drm/i915/dsi: abstract intel_dsi_tlpx_ns()
12e0bd55c174 drm/i915/dsi: abstract dphy parameter init
675f0426321d drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
f6f1e7f158e5 drm/i915: make encoder enable and disable hooks optional

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10486/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915/icl: dsi enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/51011/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4995_full -> Patchwork_10486_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10486_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10486_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10486_full:

  === IGT changes ===

    ==== Warnings ====

    igt@perf_pmu@rc6:
      shard-kbl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10486_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927, fdo#106886)

    igt@gem_exec_schedule@pi-ringfull-blt:
      shard-skl:          NOTRUN -> FAIL (fdo#103158)

    igt@gem_exec_schedule@pi-ringfull-bsd:
      shard-apl:          NOTRUN -> FAIL (fdo#103158)

    igt@kms_color@pipe-a-legacy-gamma:
      shard-apl:          PASS -> FAIL (fdo#104782, fdo#108145)

    igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
      shard-glk:          PASS -> DMESG-WARN (fdo#105763, fdo#106538)

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
      shard-apl:          SKIP -> INCOMPLETE (fdo#103927)

    igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-blt:
      shard-snb:          SKIP -> INCOMPLETE (fdo#105411)

    igt@kms_plane@plane-position-covered-pipe-b-planes:
      shard-glk:          PASS -> FAIL (fdo#103166) +3

    igt@testdisplay:
      shard-glk:          PASS -> INCOMPLETE (fdo#103359, k.org#198133)

    
    ==== Possible fixes ====

    igt@kms_atomic_interruptible@legacy-cursor:
      shard-kbl:          DMESG-WARN (fdo#108473) -> PASS

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
      shard-hsw:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
      shard-glk:          FAIL (fdo#108145) -> PASS

    igt@kms_cursor_crc@cursor-128x42-sliding:
      shard-glk:          FAIL (fdo#103232) -> PASS +1

    igt@kms_flip@flip-vs-modeset-interruptible:
      shard-kbl:          DMESG-WARN (fdo#103313) -> PASS +2

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
      shard-apl:          FAIL (fdo#103167) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
      shard-glk:          FAIL (fdo#103167) -> PASS +1

    igt@kms_plane@plane-position-covered-pipe-a-planes:
      shard-glk:          FAIL (fdo#103166) -> PASS

    igt@kms_plane_lowres@pipe-b-tiling-none:
      shard-kbl:          DMESG-WARN (fdo#105345, fdo#103313) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-apl:          FAIL (fdo#103166) -> PASS +3

    
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
  fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108473 https://bugs.freedesktop.org/show_bug.cgi?id=108473
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4995 -> Patchwork_10486

  CI_DRM_4995: 54f2281117133d77122fe452af3ea0bd5b6161aa @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4683: 7766b1e2348b32cc8ed58a972c6fd53b20279549 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10486: 77756b23dbf159cd95e7379afb52a211d31e41bb @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10486/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx