From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 1/3] drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents Date: Thu, 04 Oct 2018 09:38:39 +0300 Message-ID: <87efd6qkr4.fsf@intel.com> References: <45789401f16fbc212da16e65cce2d5f6da8e4af1.1538582156.git.jani.nikula@intel.com> <20181003182620.GB2585@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id E0A8A6E1BC for ; Thu, 4 Oct 2018 06:38:46 +0000 (UTC) In-Reply-To: <20181003182620.GB2585@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Manasi Navare Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org T24gV2VkLCAwMyBPY3QgMjAxOCwgTWFuYXNpIE5hdmFyZSA8bWFuYXNpLmQubmF2YXJlQGludGVs LmNvbT4gd3JvdGU6Cj4gVGhpcyBwYXRjaCBzZXQgb25seSB1cGRhdGVzIHRoZW0gaW4gY2FzZSBv ZiBmZXcgcmVnaXN0ZXJzLgo+IEFsbCB0aGUgb3RoZXIgTUFTS1MgYW5kIFNISUZUUyBjbGVhbiB1 cCBmb3IgYWxsIGk5MTUgcmVnaXN0ZXJzCj4gYXMgYSBmb2xsb3cgdXAgcmlnaHQ/CgpMZXQncyBz ZWUgaWYgd2UgY2FuIGFncmVlIHRoaXMgaXMgdGhlIGRpcmVjdGlvbiB3ZSB3YW50IHRvIGdvIGZp cnN0LgoKQlIsCkphbmkuCgotLSAKSmFuaSBOaWt1bGEsIEludGVsIE9wZW4gU291cmNlIEdyYXBo aWNzIENlbnRlcgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f XwpJbnRlbC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcK aHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK