From: Jani Nikula <jani.nikula@linux.intel.com>
To: vathsala nagaraju <vathsala.nagaraju@intel.com>,
rodrigo.vivi@intel.com, dri-devel@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Puthikorn Voravootivat <puthik@chromium.org>
Subject: Re: [PATCH 1/2] drm/dp: Add defines for latency in sink
Date: Mon, 25 Sep 2017 11:23:26 +0300 [thread overview]
Message-ID: <87efqv5gqp.fsf@nikula.org> (raw)
In-Reply-To: <1506126883-22800-1-git-send-email-vathsala.nagaraju@intel.com>
On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> include/drm/drm_dp_helper.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 11c39f1..846004e6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -735,6 +735,9 @@
> # define DP_PSR_SINK_INTERNAL_ERROR 7
> # define DP_PSR_SINK_STATE_MASK 0x07
>
> +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
> +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
For the DP spec, please don't invent the names, use the ones from the
spec. At most drop excess stuff from the end.
#define DP_SYNCHRONIZATION_LATENCY_IN_SINK
# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
# define DP_MAX_RESYNC_FRAME_COUNT_MASK
And while at it, please add the full register contents.
BR,
Jani.
> +
> #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2017-09-25 8:23 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-23 0:34 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-23 0:34 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-25 8:30 ` [Intel-gfx] " Jani Nikula
2017-09-25 9:10 ` vathsala nagaraju
2017-09-25 16:57 ` Rodrigo Vivi
2017-09-23 0:59 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink Patchwork
2017-09-23 1:56 ` ✓ Fi.CI.IGT: " Patchwork
2017-09-25 8:23 ` Jani Nikula [this message]
2017-09-25 9:01 ` [PATCH 1/2] " vathsala nagaraju
2017-09-25 17:05 ` Rodrigo Vivi
2017-09-25 17:34 ` [Intel-gfx] " Jani Nikula
2017-09-26 8:03 ` Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2017-09-26 9:59 vathsala nagaraju
2017-09-20 14:32 vathsala nagaraju
2017-09-20 22:07 ` Rodrigo Vivi
2017-09-21 14:42 ` Rodrigo Vivi
2017-09-26 5:11 ` Daniel Vetter
2017-09-26 17:37 ` Puthikorn Voravootivat
2017-09-26 20:37 ` Puthikorn Voravootivat
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