From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com, Deepak M <m.deepak@intel.com>
Subject: Re: [GLK MIPI DSI V5 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
Date: Thu, 16 Feb 2017 17:15:34 +0200 [thread overview]
Message-ID: <87efyymajt.fsf@intel.com> (raw)
In-Reply-To: <1487078180-15147-7-git-send-email-madhav.chauhan@intel.com>
On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Register MIPI_CLOCK_CTRL is applicable only
> for BXT platform. Future platform have other
> registers to program the escape clock dividers.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++++++++++++++----------
> 1 file changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index e6383cb..aadf7de 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -493,8 +493,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
> POSTING_READ(BXT_DSI_PLL_CTL);
>
> /* Program TX, RX, Dphy clocks */
> - for_each_dsi_port(port, intel_dsi->ports)
> - bxt_dsi_program_clocks(encoder->base.dev, port, config);
> + if (IS_BROXTON(dev_priv)) {
> + for_each_dsi_port(port, intel_dsi->ports)
> + bxt_dsi_program_clocks(encoder->base.dev, port, config);
> + }
>
> /* Enable DSI PLL */
> val = I915_READ(BXT_DSI_PLL_ENABLE);
> @@ -558,19 +560,22 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
> bxt_disable_dsi_pll(encoder);
> }
>
> -static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
> + enum port port)
> {
> u32 tmp;
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> /* Clear old configurations */
> - tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> - tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
> - I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> + if (IS_BROXTON(dev_priv)) {
> + tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
> + I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> + }
> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> }
>
> @@ -579,7 +584,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> if (IS_GEN9_LP(dev_priv))
> - bxt_dsi_reset_clocks(encoder, port);
> + gen9lp_dsi_reset_clocks(encoder, port);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_reset_clocks(encoder, port);
> }
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx mailing list
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next prev parent reply other threads:[~2017-02-16 15:15 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-14 13:16 [GLK MIPI DSI V5 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-02-14 13:16 ` [GLK MIPI DSI V5 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-02-16 14:47 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
2017-02-16 14:50 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2017-02-16 15:07 ` Jani Nikula
2017-02-17 5:23 ` Chauhan, Madhav
2017-02-14 13:16 ` [GLK MIPI DSI V5 4/8] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2017-02-16 15:18 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2017-02-16 15:13 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2017-02-16 15:15 ` Jani Nikula [this message]
2017-02-14 13:16 ` [GLK MIPI DSI V5 7/8] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2017-02-14 13:16 ` [GLK MIPI DSI V5 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
2017-02-14 16:32 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev5) Patchwork
2017-02-16 15:19 ` Jani Nikula
2017-02-16 16:05 ` Chauhan, Madhav
2017-02-16 18:14 ` Jani Nikula
2017-02-17 7:36 ` Chauhan, Madhav
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