From mboxrd@z Thu Jan 1 00:00:00 1970 From: Francisco Jerez Subject: Re: [PATCH v3 1/3] drm/i915/gen9: Clean up MOCS table definitions Date: Fri, 01 Jul 2016 14:47:16 -0700 Message-ID: <87eg7dyqsb.fsf@riseup.net> References: <1467380406-11954-1-git-send-email-imre.deak@intel.com> <1467380406-11954-2-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0016330960==" Return-path: Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3632A6E1C3 for ; Fri, 1 Jul 2016 21:49:29 +0000 (UTC) In-Reply-To: <1467380406-11954-2-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak , intel-gfx@lists.freedesktop.org Cc: Eero Tamminen List-Id: intel-gfx@lists.freedesktop.org --===============0016330960== Content-Type: multipart/signed; boundary="==-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --==-=-= Content-Type: multipart/mixed; boundary="=-=-=" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Imre, Imre Deak writes: > Use named struct initializers for clarity. Also fix the target cache > definition to reflect its role in GEN9 onwards. On GEN8 a TC value of 0 > meant ELLC but on GEN9+ it means the TC and LRU controls are taken from > the PTE. > I vaguely recall bringing up this apparent inconsistency with the hardware spec during review of the original series of patches programming the MOCS tables. IIRC TC value 0 behaved as ELLC-only on the simulator, but the hardware docs claimed it would take the target cache from the PTE controls, not sure what the real hardware actually does. Maybe Peter can confirm whether this was intentional? > No functional change, igt/gem_mocs_settings still passing after this > change. > > v2: (Chris) > - Add back the hexa literals for the entries. > Add note that igt/gem_mocs_settings still passes. > > CC: Rong R Yang > CC: Yakui Zhao > CC: Chris Wilson > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_mocs.c | 88 +++++++++++++++++++++++++++------= ------ > 1 file changed, 61 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/int= el_mocs.c > index 3c1482b..d36e609 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -66,9 +66,10 @@ struct drm_i915_mocs_table { > #define L3_WB 3 >=20=20 > /* Target cache */ > -#define ELLC 0 > -#define LLC 1 > -#define LLC_ELLC 2 > +#define LE_TC_PAGETABLE 0 > +#define LE_TC_LLC 1 > +#define LE_TC_LLC_ELLC 2 > +#define LE_TC_LLC_ELLC_ALT 3 >=20=20 > /* > * MOCS tables > @@ -96,34 +97,67 @@ struct drm_i915_mocs_table { > * end. > */ > static const struct drm_i915_mocs_entry skylake_mocs_table[] =3D { > - /* { 0x00000009, 0x0010 } */ > - { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) | > - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), > - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) }, > - /* { 0x00000038, 0x0030 } */ > - { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | > - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), > - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, > - /* { 0x0000003b, 0x0030 } */ > - { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | > - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), > - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) } > + { /* 0x00000009 */ > + .control_value =3D LE_CACHEABILITY(LE_UC) | > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0), > + > + /* 0x0010 */ > + .l3cc_value =3D L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + { > + /* 0x00000038 */ > + .control_value =3D LE_CACHEABILITY(LE_PAGETABLE) | > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0), > + /* 0x0030 */ > + .l3cc_value =3D L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + { > + /* 0x0000003b */ > + .control_value =3D LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0), > + /* 0x0030 */ > + .l3cc_value =3D L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > }; >=20=20 > /* NOTE: the LE_TGT_CACHE is not used on Broxton */ > static const struct drm_i915_mocs_entry broxton_mocs_table[] =3D { > - /* { 0x00000009, 0x0010 } */ > - { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) | > - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), > - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) }, > - /* { 0x00000038, 0x0030 } */ > - { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | > - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), > - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, > - /* { 0x0000003b, 0x0030 } */ > - { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | > - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), > - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) } > + { > + /* 0x00000009 */ > + .control_value =3D LE_CACHEABILITY(LE_UC) | > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0), > + > + /* 0x0010 */ > + .l3cc_value =3D L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + { > + /* 0x00000038 */ > + .control_value =3D LE_CACHEABILITY(LE_PAGETABLE) | > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0), > + > + /* 0x0030 */ > + .l3cc_value =3D L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + { > + /* 0x0000003b */ > + .control_value =3D LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0), > + > + /* 0x0030 */ > + .l3cc_value =3D L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > }; >=20=20 > /** > --=20 > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx --=-=-=-- --==-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iF4EAREIAAYFAld25OQACgkQg5k4nX1Sv1vmnAD/U+tTz4OKR4JqHnpqG/C3ICDI u9T/0iCv3nB3Sqh+7uABAJYwByPN+dyf+rjp44urK9AMF1Xuo8Iuv/X3ZFFAwDB+ =KUMq -----END PGP SIGNATURE----- --==-=-=-- --===============0016330960== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============0016330960==--