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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Nick Hoath <nicholas.hoath@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915/bxt: Clean up bxt_init_clock_gating
Date: Mon, 29 Jun 2015 17:29:45 +0300	[thread overview]
Message-ID: <87egkupoyu.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1435583252-29608-4-git-send-email-nicholas.hoath@intel.com>

Nick Hoath <nicholas.hoath@intel.com> writes:

> Add stepping check for A0 workarounds, and remove the associated
> FIXME tags.
> Split out unrelated WAs for later condition checking.
>
> v2: Fixed format (PeterL)
> v3: Corrected stepping check for WaDisableSDEUnitClockGating
>     - Ignoring comment, following hardware spec instead. (ChrisH)
>     Added description for TILECTL setting (JonB)
>
> Cc: Peter Lawthers <peter.lawthers@intel.com>
> Cc: Chris Harris <chris.harris@intel.com>
> Cc: Jon Bloomfield <jon.bloomfield@intel.com>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 26ef146..86a4ced 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -115,18 +115,24 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  
>  	gen9_init_clock_gating(dev);
>  
> +	/* WaDisableSDEUnitClockGating:bxt */
> +	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
>  	/*
>  	 * FIXME:
> -	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>  	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
>  	 */
> -	 /* WaDisableSDEUnitClockGating:bxt */
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
>  		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>  

I guess you decided not to combine the writes due to FIXME.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>


> -	/* FIXME: apply on A0 only */
> -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
> +	if (INTEL_REVID(dev) == BXT_REVID_A0) {
> +		/*
> +		 * Hardware specification requires this bit to be
> +		 * set to 1 for A0
> +		 */
> +		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
> +	}
>  }
>  
>  static void i915_pineview_get_mem_freq(struct drm_device *dev)
> -- 
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2015-06-29 14:30 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-29 13:07 [PATCH 1/4] drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable Nick Hoath
2015-06-29 13:07 ` [PATCH 2/4] drm/i915/bxt: Enable WaDSRefCountFullforceMissDisable Nick Hoath
2015-06-29 13:07 ` [PATCH 3/4] drm/i915/bxt: Enable WaOCLCoherentLineFlush Nick Hoath
2015-06-29 13:07 ` [PATCH 4/4] drm/i915/bxt: Clean up bxt_init_clock_gating Nick Hoath
2015-06-29 14:29   ` Mika Kuoppala [this message]
2015-09-07 13:55     ` Nick Hoath
2015-09-07 16:19       ` Daniel Vetter
2015-06-30  2:56   ` shuang.he
2015-06-29 14:08 ` [PATCH 1/4] drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable Mika Kuoppala
2015-06-29 14:19   ` Nick Hoath
2015-06-29 14:44     ` Mika Kuoppala

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