From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Arun Siluvery <arun.siluvery@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor
Date: Tue, 07 Apr 2015 17:03:32 +0300 [thread overview]
Message-ID: <87egnwc9xn.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1428411693-27889-1-git-send-email-arun.siluvery@linux.intel.com>
Arun Siluvery <arun.siluvery@linux.intel.com> writes:
> According to Spec this is a reserved bit for Gen9+ and should not be set.
>
> Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 1c3834fc..cfc73ea 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -265,7 +265,8 @@ static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
>
> desc = GEN8_CTX_VALID;
> desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
> - desc |= GEN8_CTX_L3LLC_COHERENT;
> + if (IS_GEN8(ctx_obj->base.dev))
> + desc |= GEN8_CTX_L3LLC_COHERENT;
> desc |= GEN8_CTX_PRIVILEGE;
> desc |= lrca;
> desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
> --
> 2.3.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2015-04-07 14:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-07 13:01 [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor Arun Siluvery
2015-04-07 14:03 ` Mika Kuoppala [this message]
2015-04-07 16:35 ` Daniel Vetter
2015-04-07 15:41 ` shuang.he
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