From: Jani Nikula <jani.nikula@linux.intel.com>
To: Andi Shyti <andi.shyti@kernel.org>
Cc: Andi Shyti <andi.shyti@linux.intel.com>,
Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
Date: Tue, 25 Feb 2025 18:11:24 +0200 [thread overview]
Message-ID: <87frk257ir.fsf@intel.com> (raw)
In-Reply-To: <2ueianfplrtjermhu47wufhrmws355ycleyarwagcxvyiqk5ic@t2gn7juxcqph>
On Tue, 25 Feb 2025, Andi Shyti <andi.shyti@kernel.org> wrote:
> Hi Jani,
>
> On Tue, Feb 25, 2025 at 09:52:41AM +0200, Jani Nikula wrote:
>> On Mon, 24 Feb 2025, Andi Shyti <andi.shyti@linux.intel.com> wrote:
>> > Hi Ville,
>> >
>> > On Wed, Feb 12, 2025 at 01:19:37AM +0200, Ville Syrjala wrote:
>> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>
>> >> Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
>> >> style.
>> >
>> > using REG_BIT() and co. doesn't alway make it more readable. In
>> > some of the cases below I would have preferred not to use it.
>>
>> Interesting. I read through the patch and I thought all of it was
>> good. Care to elaborate?
>
> yes you're right, I should have given an example, but I had
> already edited the e-mail and I was lazy to get it back.
>
> In any case, this is an example:
>
> - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> - GEN11_GT_S_ENA_MASK;
> + s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,
> + intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE));
>
>
> The removed line to me is clearer than the added line.
I suppose clarity could be improved with:
val = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE);
s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, val);
but in general I think REG_FIELD_GET() is better than just val & mask,
because the former handles shifting.
(For the record I'm not suggesting separating the read in this patch.)
> I'm not saying that it's not good (otherwise I wouldn't have
> r-b'ed it), I'm just saying that not always using the REG_*
> macros makes the code clearer.
>
> For consistency with the rest of the patch is anyway fine.
Agreed.
BR,
Jani.
>
> Thanks,
> Andi
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-02-25 16:11 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
2025-02-11 23:19 ` [PATCH 01/12] drm/i915: Bump RING_FAULT engine ID bits Ville Syrjala
2025-02-21 13:34 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 02/12] drm/i915: Relocate RING_FAULT bits Ville Syrjala
2025-02-21 13:45 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 03/12] drm/i915: Use REG_BIT() & co. for ring fault registers Ville Syrjala
2025-02-24 9:52 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 04/12] drm/i915: Document which RING_FAULT bits apply to which platforms Ville Syrjala
2025-02-24 9:52 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 05/12] drm/i915: Introduce RING_FAULT_VADDR_MASK Ville Syrjala
2025-02-24 9:54 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 06/12] drm/i915: Extract gen8_report_fault() Ville Syrjala
2025-02-24 10:08 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 07/12] drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits Ville Syrjala
2025-02-24 10:09 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 08/12] drm/i915: Reoder " Ville Syrjala
2025-02-24 10:13 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ " Ville Syrjala
2025-02-24 10:17 ` Andi Shyti
2025-02-25 7:52 ` Jani Nikula
2025-02-25 14:54 ` Andi Shyti
2025-02-25 16:11 ` Jani Nikula [this message]
2025-02-11 23:19 ` [PATCH 10/12] drm/i915: Reoder " Ville Syrjala
2025-02-24 10:18 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 11/12] drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers Ville Syrjala
2025-02-24 10:20 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 12/12] drm/i915: Reoder gen9+ timestamp freq register bits Ville Syrjala
2025-02-24 10:20 ` Andi Shyti
2025-02-12 0:04 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups Patchwork
2025-02-12 1:08 ` ✗ i915.CI.BAT: failure " Patchwork
2025-02-12 4:06 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev2) Patchwork
2025-02-12 4:35 ` ✗ i915.CI.BAT: failure " Patchwork
2025-02-25 0:12 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev3) Patchwork
2025-02-25 0:42 ` ✓ i915.CI.BAT: success " Patchwork
2025-02-25 3:49 ` ✓ i915.CI.Full: " Patchwork
2025-03-04 21:04 ` [PATCH 00/12] drm/i915: some GT register fixes and cleanups Andi Shyti
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87frk257ir.fsf@intel.com \
--to=jani.nikula@linux.intel.com \
--cc=andi.shyti@kernel.org \
--cc=andi.shyti@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).