From mboxrd@z Thu Jan 1 00:00:00 1970 From: Francisco Jerez Subject: Re: [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist Date: Tue, 08 Mar 2016 14:06:39 -0800 Message-ID: <87fuw0fwuo.fsf@riseup.net> References: <1457335830-30923-1-git-send-email-jordan.l.justen@intel.com> <1457335830-30923-5-git-send-email-jordan.l.justen@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0200716936==" Return-path: Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 88A206E78F for ; Tue, 8 Mar 2016 22:07:00 +0000 (UTC) In-Reply-To: <1457335830-30923-5-git-send-email-jordan.l.justen@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jordan Justen , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0200716936== Content-Type: multipart/signed; boundary="==-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --==-=-= Content-Type: multipart/mixed; boundary="=-=-=" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Jordan Justen writes: > This is needed for the Mesa Vulkan driver on Haswell. > > Signed-off-by: Jordan Justen Reviewed-by: Francisco Jerez > --- > drivers/gpu/drm/i915/i915_cmd_parser.c | 16 ++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i91= 5/i915_cmd_parser.c > index ba01836..e1608da 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -475,6 +475,22 @@ static const struct drm_i915_reg_descriptor gen7_ren= der_regs[] =3D { > }; >=20=20 > static const struct drm_i915_reg_descriptor hsw_render_regs[] =3D { > + REG64_IDX(HSW_CS_GPR, 0), > + REG64_IDX(HSW_CS_GPR, 1), > + REG64_IDX(HSW_CS_GPR, 2), > + REG64_IDX(HSW_CS_GPR, 3), > + REG64_IDX(HSW_CS_GPR, 4), > + REG64_IDX(HSW_CS_GPR, 5), > + REG64_IDX(HSW_CS_GPR, 6), > + REG64_IDX(HSW_CS_GPR, 7), > + REG64_IDX(HSW_CS_GPR, 8), > + REG64_IDX(HSW_CS_GPR, 9), > + REG64_IDX(HSW_CS_GPR, 10), > + REG64_IDX(HSW_CS_GPR, 11), > + REG64_IDX(HSW_CS_GPR, 12), > + REG64_IDX(HSW_CS_GPR, 13), > + REG64_IDX(HSW_CS_GPR, 14), > + REG64_IDX(HSW_CS_GPR, 15), > REG32(HSW_SCRATCH1, > .mask =3D ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, > .value =3D 0), > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index f76cbf3..5ba7761 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -586,6 +586,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t re= g) > #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) > #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) >=20=20 > +/* There are the 16 64-bit CS General Purpose Registers */ > +#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) > +#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) > + > #define OACONTROL _MMIO(0x2360) >=20=20 > #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 > --=20 > 2.7.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx --=-=-=-- --==-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iF4EAREIAAYFAlbfTO8ACgkQg5k4nX1Sv1vb/AEAh8H+5SRFYnveZ+iOpMB1zW8f xCwvy330azNXX6BfqCMA/izBPY9ysbf5HZojQdt3XjWSIx+tOeh9ydiTkpN1JctX =06py -----END PGP SIGNATURE----- --==-=-=-- --===============0200716936== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============0200716936==--