Re: [PATCH 26/43] drm/i915: Protect register macro arguments

Jesse Barnes
2015-10-12T16:02:30Z

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Always put parens around macro argument evaluations.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 92 ++++++++++++++++++++---------------------
> 1 file changed, 46 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0216771..21d49e7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -429,7 +429,7 @@
> #define ASYNC_FLIP (1<<22)
> #define DISPLAY_PLANE_A (0<<20)
> #define DISPLAY_PLANE_B (1<<20)
> -#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
> +#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
> #define PIPE_CONTROL_FLUSH_L3 (1<<27)
> #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
> #define PIPE_CONTROL_MMIO_WRITE (1<<23)
> @@ -1250,7 +1250,7 @@ enum skl_disp_power_wells {
> #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
> #define PORT_PLL_DCO_AMP_DEFAULT 15
> #define PORT_PLL_DCO_AMP_MASK 0x3c00
> -#define PORT_PLL_DCO_AMP(x) (x<<10)
> +#define PORT_PLL_DCO_AMP(x) ((x)<<10)
> #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
> _PORT_PLL_0_B, \
> _PORT_PLL_0_C)
> @@ -1540,8 +1540,8 @@ enum skl_disp_power_wells {
> #define RENDER_HWS_PGA_GEN7 (0x04080)
> #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
> #define RING_FAULT_GTTSEL_MASK (1<<11)
> -#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
> -#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
> +#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
> +#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
> #define RING_FAULT_VALID (1<<0)
> #define DONE_REG 0x40b0
> #define GEN8_PRIVATE_PAT_LO 0x40e0
> @@ -1626,9 +1626,9 @@ enum skl_disp_power_wells {
> #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
> #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
> #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
> -#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
> +#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
> #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
> -#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
> +#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
>
> #define GEN8_FAULT_TLB_DATA0 0x04b10
> #define GEN8_FAULT_TLB_DATA1 0x04b14
> @@ -1689,8 +1689,8 @@ enum skl_disp_power_wells {
> #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
> #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
> #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
> -#define GEN9_IZ_HASHING_MASK(slice) (0x3 << (slice * 2))
> -#define GEN9_IZ_HASHING(slice, val) ((val) << (slice * 2))
> +#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
> +#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
>
> #define GFX_MODE 0x02520
> #define GFX_MODE_GEN7 0x0229c
> @@ -2828,21 +2828,21 @@ enum skl_disp_power_wells {
> * doesn't need saving on GT1
> */
> #define CXT_SIZE 0x21a0
> -#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
> -#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
> -#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
> -#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
> -#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
> +#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
> +#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
> +#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
> +#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
> +#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
> #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
> GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
> GEN6_CXT_PIPELINE_SIZE(cxt_reg))
> #define GEN7_CXT_SIZE 0x21a8
> -#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
> -#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
> -#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
> -#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
> -#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
> -#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
> +#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
> +#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
> +#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
> +#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
> +#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
> +#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
> #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
> GEN7_CXT_VFSTATE_SIZE(ctx_reg))
> /* Haswell does have the CXT_SIZE register however it does not appear to be
> @@ -5173,18 +5173,18 @@ enum skl_disp_power_wells {
> #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
> #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
>
> -#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> -#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> -#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> -#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> -#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> -#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
> -#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
> -#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
> -#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> -#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
> -#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
> -#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
> +#define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
>
> /*
> * CHV pipe B sprite CSC
> @@ -5530,7 +5530,7 @@ enum skl_disp_power_wells {
> #define PS_SCALER_MODE_DYN (0 << 28)
> #define PS_SCALER_MODE_HQ (1 << 28)
> #define PS_PLANE_SEL_MASK (7 << 25)
> -#define PS_PLANE_SEL(plane) ((plane + 1) << 25)
> +#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
> #define PS_FILTER_MASK (3 << 23)
> #define PS_FILTER_MEDIUM (0 << 23)
> #define PS_FILTER_EDGE_ENHANCE (2 << 23)
> @@ -5695,7 +5695,7 @@ enum skl_disp_power_wells {
> #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
> #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
> #define DE_PIPEA_VBLANK_IVB (1<<0)
> -#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
> +#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
>
> #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
> #define MASTER_INTERRUPT_ENABLE (1<<31)
> @@ -5719,7 +5719,7 @@ enum skl_disp_power_wells {
> #define GEN8_DE_PIPE_C_IRQ (1<<18)
> #define GEN8_DE_PIPE_B_IRQ (1<<17)
> #define GEN8_DE_PIPE_A_IRQ (1<<16)
> -#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
> +#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
> #define GEN8_GT_VECS_IRQ (1<<6)
> #define GEN8_GT_PM_IRQ (1<<4)
> #define GEN8_GT_VCS2_IRQ (1<<3)
> @@ -5763,7 +5763,7 @@ enum skl_disp_power_wells {
> #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
> #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
> #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
> -#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p))
> +#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
> #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
> (GEN8_PIPE_CURSOR_FAULT | \
> GEN8_PIPE_SPRITE_FAULT | \
> @@ -6022,7 +6022,7 @@ enum skl_disp_power_wells {
> #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
> #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
> #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
> -#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
> +#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
>
> /* digital port hotplug */
> #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
> @@ -6133,9 +6133,9 @@ enum skl_disp_power_wells {
> #define PCH_SSC4_AUX_PARMS 0xc6214
>
> #define PCH_DPLL_SEL 0xc7000
> -#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
> +#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
> #define TRANS_DPLLA_SEL(pipe) 0
> -#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
> +#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
>
> /* transcoder */
>
> @@ -7295,7 +7295,7 @@ enum skl_disp_power_wells {
> #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
> /* For each transcoder, we need to select the corresponding port clock */
> #define TRANS_CLK_SEL_DISABLED (0x0<<29)
> -#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
> +#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
>
> #define TRANSA_MSA_MISC 0x60410
> #define TRANSB_MSA_MISC 0x61410
> @@ -7368,10 +7368,10 @@ enum skl_disp_power_wells {
>
> /* DPLL control2 */
> #define DPLL_CTRL2 0x6C05C
> -#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
> +#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
> #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
> #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
> -#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
> +#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
> #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
>
> /* DPLL Status */
> @@ -7384,23 +7384,23 @@ enum skl_disp_power_wells {
> #define DPLL3_CFGCR1 0x6C050
> #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
> #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
> -#define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
> +#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
> #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
>
> #define DPLL1_CFGCR2 0x6C044
> #define DPLL2_CFGCR2 0x6C04C
> #define DPLL3_CFGCR2 0x6C054
> #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
> -#define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
> -#define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
> +#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
> +#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
> #define DPLL_CFGCR2_KDIV_MASK (3<<5)
> -#define DPLL_CFGCR2_KDIV(x) (x<<5)
> +#define DPLL_CFGCR2_KDIV(x) ((x)<<5)
> #define DPLL_CFGCR2_KDIV_5 (0<<5)
> #define DPLL_CFGCR2_KDIV_2 (1<<5)
> #define DPLL_CFGCR2_KDIV_3 (2<<5)
> #define DPLL_CFGCR2_KDIV_1 (3<<5)
> #define DPLL_CFGCR2_PDIV_MASK (7<<2)
> -#define DPLL_CFGCR2_PDIV(x) (x<<2)
> +#define DPLL_CFGCR2_PDIV(x) ((x)<<2)
> #define DPLL_CFGCR2_PDIV_1 (0<<2)
> #define DPLL_CFGCR2_PDIV_2 (1<<2)
> #define DPLL_CFGCR2_PDIV_3 (2<<2)
>

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>