Re: [PATCH 4/9] drm/i915: Pixel Clock and pixel overlap related changes for dual link Configuration

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 24 Sep 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>  drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>  drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>  drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
>  5 files changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 922d807..3ed5774 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5662,6 +5662,10 @@ enum punit_power_well {
>  #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
>  #define VLV_PWRDWNUPCTL				0xA294
>  
> +#define VLV_CHICKEN_3				0x7040C
> +#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
> +#define  PIXEL_OVERLAP_CNT_SHIFT		30
> +
>  #define GEN6_PMISR				0x44020
>  #define GEN6_PMIMR				0x44024 /* rps_lock */
>  #define GEN6_PMIIR				0x44028
> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
> index 7603765..39dfb65 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -798,7 +798,8 @@ struct mipi_config {
>  #define DUAL_LINK_PIXEL_ALT	2
>  	u16 dual_link:2;
>  	u16 lane_cnt:2;
> -	u16 rsvd3:12;
> +	u16 pixel_overlap:3;
> +	u16 rsvd3:9;
>  
>  	u16 rsvd4;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 3b1890e..583c7fd 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -116,6 +116,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  					<< DUAL_LINK_MODE_SHIFT;
>  		port_control |= pipe ? LANE_CONFIGURATION_DUAL_LINK_B :
>  					LANE_CONFIGURATION_DUAL_LINK_A;
> +
> +		if (intel_dsi->dual_link & MIPI_DUAL_LINK_FRONT_BACK) {

It's really confusing to treat ->dual_link as a bit mask when it's not.

> +			temp = I915_READ(VLV_CHICKEN_3);
> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +				intel_dsi->pixel_overlap <<
> +				PIXEL_OVERLAP_CNT_SHIFT;
> +			I915_WRITE(VLV_CHICKEN_3, temp);
> +		}
>  		/*For Port A */
>  		temp = I915_READ(MIPI_PORT_CTRL(0));
>  		temp = temp | port_control;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 950ab41..7fac460 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -28,6 +28,11 @@
>  #include <drm/drm_crtc.h>
>  #include "intel_drv.h"
>  
> +/* Dual Link support */
> +#define MIPI_DUAL_LINK_NONE		0
> +#define MIPI_DUAL_LINK_FRONT_BACK	1
> +#define MIPI_DUAL_LINK_PIXEL_ALT	2
> +

Spread the word, using the word "MIPI" for "DSI" feels like saying I
have an "embedded VESA" display on my laptop. Really.

>  struct intel_dsi_device {
>  	unsigned int panel_id;
>  	const char *name;
> @@ -102,6 +107,7 @@ struct intel_dsi {
>  
>  	u8 escape_clk_div;
>  	u8 dual_link;
> +	u8 pixel_overlap;
>  	u32 port_bits;
>  	u32 bw_timer;
>  	u32 dphy_reg;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index d424ebc..8bc911b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -284,6 +284,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>  	intel_dsi->port = 0;
>  	intel_dsi->dual_link = mipi_config->dual_link;
> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>  
>  	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>  		bits_per_pixel = 18;
> @@ -303,6 +304,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  
>  	pclk = mode->clock;
>  
> +	/* In dual link mode each port needs half of pixel clock */
> +	if (intel_dsi->dual_link) {
> +		pclk = pclk / 2;
> +
> +		/* we can enable pixel_overlap if needed by panel. In this
> +		 * case we need to increase the pixelclock for extra pixels
> +		 */
> +		if (intel_dsi->dual_link & MIPI_DUAL_LINK_FRONT_BACK) {
> +			pclk += DIV_ROUND_UP(mode->vtotal *
> +						intel_dsi->pixel_overlap *
> +						60, 1000);
> +		}
> +	}
> +
>  	/* Burst Mode Ratio
>  	 * Target ddr frequency from VBT / non burst ddr freq
>  	 * multiply by 100 to preserve remainder
> @@ -497,6 +512,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>  						"disabled" : "enabled");
>  	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
> +	if (intel_dsi->dual_link == MIPI_DUAL_LINK_FRONT_BACK)
> +		DRM_DEBUG_KMS("Dual link: MIPI_DUAL_LINK_FRONT_BACK\n");
> +	else if (intel_dsi->dual_link == MIPI_DUAL_LINK_PIXEL_ALT)
> +		DRM_DEBUG_KMS("Dual link: MIPI_DUAL_LINK_PIXEL_ALT\n");
> +	else
> +		DRM_DEBUG_KMS("Dual link: NONE\n");
>  	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>  	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>  	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
> -- 
> 1.7.9.5
>
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-- 
Jani Nikula, Intel Open Source Technology Center