From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv Date: Fri, 11 Jul 2014 17:50:25 +0300 Message-ID: <87fvi8j6fi.fsf@gaia.fi.intel.com> References: <1404978387-28180-1-git-send-email-deepak.s@linux.intel.com> <1404978387-28180-5-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 834CF6E83D for ; Fri, 11 Jul 2014 07:50:37 -0700 (PDT) In-Reply-To: <1404978387-28180-5-git-send-email-deepak.s@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org deepak.s@linux.intel.com writes: > From: Deepak S > > We need mem_freq or cz clock for freq/opcode conversion > > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++ > 3 files changed, 36 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index bce4654..568b39c 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -932,6 +932,7 @@ struct intel_gen6_power_mgmt { > u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ > u8 rp1_freq; /* "less than" RP0 power/freqency */ > u8 rp0_freq; /* Non-overclocked max frequency. */ > + u32 cz_freq; > > u32 ei_interrupt_count; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 490f031..e533efa 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5541,6 +5541,12 @@ enum punit_power_well { > GEN6_PM_RP_DOWN_THRESHOLD | \ > GEN6_PM_RP_DOWN_TIMEOUT) > > +#define CHV_CZ_CLOCK_FREQ_MODE_200 200 > +#define CHV_CZ_CLOCK_FREQ_MODE_267 267 > +#define CHV_CZ_CLOCK_FREQ_MODE_320 320 > +#define CHV_CZ_CLOCK_FREQ_MODE_333 333 > +#define CHV_CZ_CLOCK_FREQ_MODE_400 400 > + No need to define these in my opinion as it is 1:1. Just use the numbers straight. > #define GEN7_GT_SCRATCH_BASE 0x4F100 > #define GEN7_GT_SCRATCH_REG_NUM 8 > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9dfebab..6c19ce5 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5706,6 +5706,35 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > static void cherryview_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > + u32 val; > + > + mutex_lock(&dev_priv->rps.hw_lock); > + val = vlv_punit_read(dev_priv, CCK_FUSE_REG); s/punit/cck (?) With the changes mentioned above: Reviewed-by: Mika Kuoppala > + mutex_unlock(&dev_priv->rps.hw_lock); > + switch ((val >> 2) & 0x7) { > + case 0: > + case 1: > + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200; > + dev_priv->mem_freq = 1600; > + break; > + case 2: > + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267; > + dev_priv->mem_freq = 1600; > + break; > + case 3: > + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333; > + dev_priv->mem_freq = 2000; > + break; > + case 4: > + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320; > + dev_priv->mem_freq = 1600; > + break; > + case 5: > + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400; > + dev_priv->mem_freq = 1600; > + break; > + } > + DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > > I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx