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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Garg, Nemesa" <nemesa.garg@intel.com>,
	"Golani,
	Mitulkumar Ajitkumar" <mitulkumar.ajitkumar.golani@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: RE: [PATCH v3] drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock
Date: Thu, 20 Jun 2024 16:36:20 +0300	[thread overview]
Message-ID: <87h6dnenxn.fsf@intel.com> (raw)
In-Reply-To: <IA1PR11MB6467CD43E3FF6D50E2775B99E3C82@IA1PR11MB6467.namprd11.prod.outlook.com>

On Thu, 20 Jun 2024, "Garg, Nemesa" <nemesa.garg@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mitul
>> Golani
>> Sent: Wednesday, June 19, 2024 4:08 PM
>> To: intel-gfx@lists.freedesktop.org
>> Subject: [PATCH v3] drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock
>> 
>> The dispcnlunit1_cp_xosc_clk should be de-asserted in display off and only
>> asserted in display on. But during observation it found clk remains active in display
>> OFF. As workaround, Display driver shall execute set-reset sequence at the end of
>> the Initialize Sequence.
>> 
>> Wa_15013987218
>> 
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index e288a1b21d7e..aef54c1a2ba9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -1704,6 +1704,14 @@ static void icl_display_core_init(struct
>> drm_i915_private *dev_priv,
>>  	/* Wa_14011503030:xelpd */
>>  	if (DISPLAY_VER(dev_priv) == 13)
>>  		intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK,
>> ~0);
>> +
>> +	/* Wa_15013987218 */
>> +	if (DISPLAY_VER(dev_priv) == 20) {
>> +		intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D,
>> +			       PCH_GMBUSUNIT_CLOCK_GATE_DISABLE);
>
> Nit:  we can replace the above statement with this intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE) so that code consistency can be maintained in the code block.
> otherwise LGTM.

It's not just about consistency. Are you even sure you can erase
everything else in the register here?

BR,
Jani.

>
>> +		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
>> +			     PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0);
>> +	}
>>  }
>> 
>>  static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
>> --
>> 2.45.2
>

-- 
Jani Nikula, Intel

  reply	other threads:[~2024-06-20 13:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-19 10:38 [PATCH v3] drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock Mitul Golani
2024-06-19 14:55 ` ✓ Fi.CI.BAT: success for drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock (rev2) Patchwork
2024-06-19 17:06 ` ✓ Fi.CI.IGT: " Patchwork
2024-06-20  4:36 ` [PATCH v3] drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock Garg, Nemesa
2024-06-20 13:36   ` Jani Nikula [this message]
2024-07-08  4:17 ` Kandpal, Suraj

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