From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC40CC77B7C for ; Fri, 12 May 2023 23:20:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D522910E5A8; Fri, 12 May 2023 23:20:39 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 54E0210E5A8 for ; Fri, 12 May 2023 23:20:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683933637; x=1715469637; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=mbihKR26CuTmcca6KMEtakB4LlPVyv781s07fjj9wpU=; b=m+vLg2lnOHPaX7h8JIZ9bLZchGH6d3yHIZKM5KsvrlqZrWu5EAPZ6/yY dSzo18+ZhFTcQhJ7YF58jKVDken2fXthC7yF8fReladTnnHlY0mqzVvpC lXYFVRCyT5vPdAIllnil5FRi8BQTmr/RsHj3f4DEVxRNhN3ycLI5AtMUq CjYnVS8ayBgOJIGjNKpgK/QYP27ylVPfg7Iq2YLEjLeFY8LkxldmLFy0p VDZ63MA1Nf+ioTndqNFHan42UtE+Kuqk5UTDsPX9j2Dmb8u4iFi2VMpe0 waedFGK4EwgXPxxnme/BvUQ9iiEN8xWtaQTboX/J86hJa1OEFT6+HXV1E w==; X-IronPort-AV: E=McAfee;i="6600,9927,10708"; a="354041247" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="354041247" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2023 16:20:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10708"; a="765308027" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="765308027" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.239.47]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2023 16:20:35 -0700 Date: Fri, 12 May 2023 16:20:19 -0700 Message-ID: <87h6shdtn0.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> <20230506005816.1891043-5-umesh.nerlige.ramappa@intel.com> <87ilcxdw0g.wl-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 12 May 2023 15:44:00 -0700, Umesh Nerlige Ramappa wrote: > > On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote: > > On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: > >> > > > > Hi Umesh/Tvrtko, > > > >> From: Tvrtko Ursulin > >> > >> We do not want to have timers per tile and waste CPU cycles and energy via > >> multiple wake-up sources, for a relatively un-important task of PMU > >> sampling, so keeping a single timer works well. But we also do not want > >> the first GT which goes idle to turn off the timer. > >> > >> Add some reference counting, via a mask of unparked GTs, to solve this. > >> > >> Signed-off-by: Tvrtko Ursulin > >> Signed-off-by: Umesh Nerlige Ramappa > >> --- > >> drivers/gpu/drm/i915/i915_pmu.c | 12 ++++++++++-- > >> drivers/gpu/drm/i915/i915_pmu.h | 4 ++++ > >> 2 files changed, 14 insertions(+), 2 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > >> index 2b63ee31e1b3..669a42e44082 100644 > >> --- a/drivers/gpu/drm/i915/i915_pmu.c > >> +++ b/drivers/gpu/drm/i915/i915_pmu.c > >> @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt) > >> * Signal sampling timer to stop if only engine events are enabled and > >> * GPU went idle. > >> */ > >> - pmu->timer_enabled = pmu_needs_timer(pmu, false); > >> + pmu->unparked &= ~BIT(gt->info.id); > >> + if (pmu->unparked == 0) > >> + pmu->timer_enabled = pmu_needs_timer(pmu, false); > >> > >> spin_unlock_irq(&pmu->lock); > >> } > >> @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt) > >> /* > >> * Re-enable sampling timer when GPU goes active. > >> */ > >> - __i915_pmu_maybe_start_timer(pmu); > >> + if (pmu->unparked == 0) > >> + __i915_pmu_maybe_start_timer(pmu); > >> + > >> + pmu->unparked |= BIT(gt->info.id); > >> > >> spin_unlock_irq(&pmu->lock); > >> } > >> @@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) > >> */ > >> > >> for_each_gt(gt, i915, i) { > >> + if (!(pmu->unparked & BIT(i))) > >> + continue; > >> + > > > > This is not correct. In this series we are at least sampling frequencies > > (calling frequency_sample) even when GT is parked. So these 3 lines should be > > deleted. engines_sample will get called and will return without doing > > anything if engine events are disabled. > > Not sure I understand. This is checking pmu->'un'parked bits. Sorry, my bad. Not "engines_sample will get called and will return without doing anything if engine events are disabled" but "engines_sample will get called and will return without doing anything if GT is not awake". This is the same as the previous behavior before this series. Umesh and I discussed this but writing this out in case Tvrtko takes a look. Thanks. -- Ashutosh > > > > > >> engines_sample(gt, period_ns); > >> > >> if (i == 0) /* FIXME */ > >> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h > >> index a686fd7ccedf..3a811266ac6a 100644 > >> --- a/drivers/gpu/drm/i915/i915_pmu.h > >> +++ b/drivers/gpu/drm/i915/i915_pmu.h > >> @@ -76,6 +76,10 @@ struct i915_pmu { > >> * @lock: Lock protecting enable mask and ref count handling. > >> */ > >> spinlock_t lock; > >> + /** > >> + * @unparked: GT unparked mask. > >> + */ > >> + unsigned int unparked; > >> /** > >> * @timer: Timer for internal i915 PMU sampling. > >> */ > >> -- > >> 2.36.1 > >>