From: Jani Nikula <jani.nikula@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
Date: Mon, 10 Jan 2022 13:15:47 +0200 [thread overview]
Message-ID: <87h7abaljw.fsf@intel.com> (raw)
In-Reply-To: <20220108044055.3123418-6-matthew.d.roper@intel.com>
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> It's preferable to use parameterized register macros where possible.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 977619ea839a..895939a941d6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2423,7 +2423,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (GRAPHICS_VER(i915) == 7) {
> /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> wa_masked_en(wal,
> - GFX_MODE_GEN7,
> + RING_MODE_GEN7(RENDER_RING_BASE),
> GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
>
> /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index f776c470914d..abc81cdc9e5d 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -44,7 +44,7 @@
>
> /* Raw offset is appened to each line for convenience. */
> static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
> - {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
> + {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
> {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
> {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
> {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
> @@ -76,7 +76,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
> };
>
> static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> - {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
> + {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
> {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
> {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
> {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b227a1e58f9b..7f0168ba55f2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2918,7 +2918,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
>
> #define GFX_MODE _MMIO(0x2520)
> -#define GFX_MODE_GEN7 _MMIO(0x229c)
> #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
> #define GFX_RUN_LIST_ENABLE (1 << 15)
> #define GFX_INTERRUPT_STEERING (1 << 14)
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-01-10 11:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
2022-01-10 11:20 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
2022-01-10 11:06 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD Matt Roper
2022-01-10 11:10 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
2022-01-10 11:14 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
2022-01-10 11:15 ` Jani Nikula [this message]
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header Matt Roper
2022-01-10 10:59 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY " Matt Roper
2022-01-10 11:02 ` Jani Nikula
2022-01-10 11:03 ` Jani Nikula
2022-01-08 5:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev2) Patchwork
2022-01-08 5:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-08 5:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-08 7:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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