From: Jani Nikula <jani.nikula@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@gmail.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Subject: Re: drm/i915: Make MMIO_PORT flexible.
Date: Thu, 15 Jun 2017 22:33:28 +0300 [thread overview]
Message-ID: <87h8zhxczb.fsf@intel.com> (raw)
In-Reply-To: <20170613124942.GK12629@intel.com>
On Tue, 13 Jun 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> If there's lot of these and they get used a lot then I think the best
> option might be to add some kind of phy_port_offsets[] type of thing.
> Although it seems we'd need separate offsets for the group vs.
> individual lane access.
We have that for pipe_offsets, trans_offsets, palette_offsets, and
cursor_offsets in struct intel_device_info. That's fine for some things,
a bit awkward for some others. It's a bit heavy when there are just few
registers following some scheme.
> But for just a few registers that are not used that much and are
> purely CNL specific, then I guess just using _PICK for them might be
> OK.
Yes, we definitely want to avoid _PICK when ((a) + (port)*((b)-(a))) or
similar will do.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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prev parent reply other threads:[~2017-06-15 19:33 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-08 17:05 [PATCH] drm/i915: Make MMIO_PORT flexible Rodrigo Vivi
2017-06-08 17:35 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-06-12 7:32 ` ✓ Fi.CI.BAT: success " Patchwork
2017-06-12 14:56 ` Ville Syrjälä
2017-06-12 16:28 ` Vivi, Rodrigo
2017-06-12 17:11 ` Ville Syrjälä
2017-06-12 17:26 ` Rodrigo Vivi
2017-06-13 12:49 ` Ville Syrjälä
2017-06-15 19:33 ` Jani Nikula [this message]
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