From: Jani Nikula <jani.nikula@intel.com>
To: "Chauhan, Madhav" <madhav.chauhan@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Conselvan De Oliveira,
Ander" <ander.conselvan.de.oliveira@intel.com>,
Deepak M <m.deepak@intel.com>,
"Kumar, Shobhit" <shobhit.kumar@intel.com>
Subject: Re: [GLK MIPI DSI V2 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence
Date: Tue, 27 Dec 2016 14:34:20 +0200 [thread overview]
Message-ID: <87h95p4kkz.fsf@intel.com> (raw)
In-Reply-To: <FDE0F82259988449BC0C053E4EF090C947FC38B3@BGSMSX104.gar.corp.intel.com>
On Mon, 26 Dec 2016, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Friday, December 23, 2016 7:40 PM
>> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
>> Saarinen, Jani <jani.saarinen@intel.com>; Konduru, Chandra
>> <chandra.konduru@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>> Mukherjee, Indranil <indranil.mukherjee@intel.com>; Kumar, Shobhit
>> <shobhit.kumar@intel.com>; Deepak M <m.deepak@intel.com>; Chauhan,
>> Madhav <madhav.chauhan@intel.com>
>> Subject: Re: [GLK MIPI DSI V2 3/9] drm/i915/glk: Add MIPIIO Enable/disable
>> sequence
>>
>> On Thu, 15 Dec 2016, Madhav Chauhan <madhav.chauhan@intel.com>
>> wrote:
>> > From: Deepak M <m.deepak@intel.com>
>> >
>> > v2: Addressed Jani's Review comments(renamed bit field macros)
>> >
>> > Signed-off-by: Deepak M <m.deepak@intel.com>
>> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_dsi.c | 134
>> > +++++++++++++++++++++++++++++++++++++++
>> > 1 file changed, 134 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> > b/drivers/gpu/drm/i915/intel_dsi.c
>> > index b78c686..c0697e9 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> > @@ -357,6 +357,134 @@ static bool intel_dsi_compute_config(struct
>> intel_encoder *encoder,
>> > return true;
>> > }
>> >
>> > +static void intel_dsi_disable_mipiio(struct intel_encoder *encoder) {
>> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> > + enum port port;
>> > + u32 tmp;
>> > +
>> > + /* Put the IO into reset */
>> > + tmp = I915_READ(MIPI_CTRL(PORT_A));
>> > + tmp &= ~GLK_MIPIIO_RESET_RELEASED;
>> > + I915_WRITE(MIPI_CTRL(PORT_A), tmp);
>> > +
>> > + /* Wait for MIPI PHY status bit to unset */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + if (intel_wait_for_register(dev_priv,
>> > + MIPI_CTRL(port),
>> > + GLK_PHY_STATUS_PORT_READY, 0, 20))
>> > + DRM_ERROR("PHY is not turning OFF\n");
>> > + }
>> > +
>> > + /* Clear MIPI mode */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + tmp = I915_READ(MIPI_CTRL(port));
>> > + tmp &= ~GLK_MIPIIO_ENABLE;
>> > + I915_WRITE(MIPI_CTRL(port), tmp);
>> > + }
>> > +}
>> > +
>> > +static void intel_dsi_enable_mipiio(struct intel_encoder *encoder) {
>> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> > + enum port port;
>> > + u32 tmp, val;
>> > +
>> > + /* Put the IO into reset */
>> > + tmp = I915_READ(MIPI_CTRL(PORT_A));
>> > + tmp &= ~GLK_MIPIIO_RESET_RELEASED;
>> > + I915_WRITE(MIPI_CTRL(PORT_A), tmp);
>> > +
>> > + /* Program LP Wake */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + tmp = I915_READ(MIPI_CTRL(port));
>> > + tmp &= ~GLK_LP_WAKE;
>> > + I915_WRITE(MIPI_CTRL(port), tmp);
>> > + }
>> > +
>> > + /* Set the MIPI mode */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + tmp = I915_READ(MIPI_CTRL(port));
>> > + I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
>> > + }
>> > +
>> > + /* Wait for Pwr ACK */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + if (intel_wait_for_register(dev_priv,
>> > + MIPI_CTRL(port),
>> GLK_MIPIIO_PORT_POWERED,
>> > + GLK_MIPIIO_PORT_POWERED, 20))
>> > + DRM_ERROR("Power ACK not received\n");
>> > + }
>> > +
>> > + /* Wait for MIPI PHY status bit to set */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + if (intel_wait_for_register(dev_priv,
>> > + MIPI_CTRL(port),
>> GLK_MIPIIO_PORT_POWERED,
>> > + GLK_MIPIIO_PORT_POWERED, 20))
>> > + DRM_ERROR("PHY is not ON\n");
>> > + }
>> > +
>> > + /* Get IO out of reset */
>> > + tmp = I915_READ(MIPI_CTRL(PORT_A));
>> > + I915_WRITE(MIPI_CTRL(PORT_A), tmp |
>> GLK_MIPIIO_RESET_RELEASED);
>> > +
>> > + /* Get IO out of Low power state*/
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + if (!(I915_READ(MIPI_DEVICE_READY(port)) &
>> DEVICE_READY)) {
>> > + val = I915_READ(MIPI_DEVICE_READY(port));
>> > + val &= ~ULPS_STATE_MASK;
>> > + val |= DEVICE_READY;
>> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
>> > + usleep_range(10, 15);
>> > + }
>> > +
>> > + /* Enter ULPS */
>> > + val = I915_READ(MIPI_DEVICE_READY(port));
>> > + val &= ~ULPS_STATE_MASK;
>> > + val |= (ULPS_STATE_ENTER | DEVICE_READY);
>> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
>> > +
>> > + /* Wait for ULPS Not active */
>> > + if (intel_wait_for_register(dev_priv,
>> > + MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
>> > + GLK_ULPS_NOT_ACTIVE, 20))
>> > +
>> > + /* Exit ULPS */
>> > + val = I915_READ(MIPI_DEVICE_READY(port));
>> > + val &= ~ULPS_STATE_MASK;
>> > + val |= (ULPS_STATE_EXIT | DEVICE_READY);
>> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
>> > +
>> > + /* Enter Normal Mode */
>> > + val = I915_READ(MIPI_DEVICE_READY(port));
>> > + val &= ~ULPS_STATE_MASK;
>> > + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
>> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
>> > +
>> > + tmp = I915_READ(MIPI_CTRL(port));
>> > + tmp &= ~GLK_LP_WAKE;
>> > + I915_WRITE(MIPI_CTRL(port), tmp);
>> > + }
>> > +
>> > + /* Wait for Stop state */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + if (intel_wait_for_register(dev_priv,
>> > + MIPI_CTRL(port),
>> GLK_DATA_LANE_STOP_STATE,
>> > + GLK_DATA_LANE_STOP_STATE, 20))
>> > + DRM_ERROR("Date lane not in STOP state\n");
>> > + }
>> > +
>> > + /* Wait for AFE LATCH */
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + if (intel_wait_for_register(dev_priv,
>> > + BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
>> > + AFE_LATCHOUT, 20))
>> > + DRM_ERROR("D-PHY not entering LP-11 state\n");
>> > + }
>> > +}
>> > +
>>
>> I'm wondering if these should just be GLK versions of intel_dsi_device_ready
>> and intel_dsi_clear_device_ready. It seems totally wrong that you're doing
>> device ready stuff twice on GLK...
>
> Agree. Don't need to call intel_dsi_device_ready for GLK, as device ready is already done inside enable_io.
> Will do following :
> If(!IS_GEMINILAKE(dev_priv)
> intel_dsi_device_ready(encoder);
>
>>
>>
>> > static void bxt_dsi_device_ready(struct intel_encoder *encoder) {
>> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> @@
>> > -559,6 +687,9 @@ static void intel_dsi_pre_enable(struct intel_encoder
>> > *encoder,
>> >
>> > intel_dsi_prepare(encoder, pipe_config);
>> >
>> > + if (IS_GEMINILAKE(dev_priv))
>> > + intel_dsi_enable_mipiio(encoder);
>> > +
>> > /* Panel Enable over CRC PMIC */
>> > if (intel_dsi->gpio_panel)
>> > gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); @@ -
>> 699,6
>> > +830,9 @@ static void intel_dsi_clear_device_ready(struct intel_encoder
>> *encoder)
>> > usleep_range(2000, 2500);
>> > }
>> >
>> > + if (IS_GEMINILAKE(dev_priv))
>> > + intel_dsi_disable_mipiio(encoder);
>> > +
>>
>> When you're doing enable/disable of something, they should be called from
>> the corresponding functions in the enable/disable paths. But this is just a
>> general remark, if we conclude that these should be alternative device
>> ready/unready calls instead.
>
> Yes agree, intel_dsi_disable_mipiio should be called from intel_dsi_post_disable after intel_dsi_clear_device_ready and before intel_disable_dsi_pll
> Will do these changes in next series.
I meant, how about renaming intel_dsi_enable_mipiio to
glk_dsi_device_ready, and making intel_dsi_device_ready call
glk_dsi_device_ready for GLK.
Then rename intel_dsi_clear_device_ready to vlv_dsi_clear_device_ready
and intel_dsi_disable_mipiio to glk_dsi_clear_device_ready, and add a
new intel_dsi_clear_device_ready wrapper to call
vlv_dsi_clear_device_ready for VLV/CHV/BXT, and
glk_dsi_clear_device_ready for GLK.
How does that sound?
BR,
Jani.
>>
>> BR,
>> Jani.
>>
>>
>> > intel_disable_dsi_pll(encoder);
>> > }
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2016-12-27 12:34 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-15 9:01 [GLK MIPI DSI V2 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2016-12-15 9:01 ` [GLK MIPI DSI V2 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Madhav Chauhan
2016-12-23 13:54 ` Jani Nikula
2016-12-15 9:01 ` [GLK MIPI DSI V2 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK Madhav Chauhan
2016-12-22 12:02 ` Ville Syrjälä
2016-12-22 12:28 ` Jani Nikula
2016-12-23 13:57 ` Jani Nikula
2016-12-23 19:22 ` Chauhan, Madhav
2016-12-26 12:49 ` Chauhan, Madhav
2016-12-15 9:01 ` [GLK MIPI DSI V2 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2016-12-23 14:09 ` Jani Nikula
2016-12-26 12:05 ` Chauhan, Madhav
2016-12-27 12:34 ` Jani Nikula [this message]
2016-12-27 13:32 ` Chauhan, Madhav
2016-12-27 14:47 ` Jani Nikula
2016-12-27 15:43 ` Chauhan, Madhav
2016-12-15 9:01 ` [GLK MIPI DSI V2 4/9] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2016-12-15 9:01 ` [GLK MIPI DSI V2 5/9] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2016-12-15 9:01 ` [GLK MIPI DSI V2 6/9] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2016-12-15 9:01 ` [GLK MIPI DSI V2 7/9] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2016-12-15 9:01 ` [GLK MIPI DSI V2 8/9] drm/i915/glk: Program dphy param reg " Madhav Chauhan
2016-12-15 9:01 ` [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
2016-12-22 11:39 ` Jani Nikula
2016-12-22 13:16 ` Chauhan, Madhav
2016-12-22 13:43 ` Jani Nikula
2016-12-22 15:43 ` Chauhan, Madhav
2016-12-15 9:45 ` ✓ Fi.CI.BAT: success for GLK MIPI DSI VIDEO MODE PATCHES (rev2) Patchwork
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