Re: [PATCH 01/14] drm/i915: Parametrize PANEL_PORT_SELECT_VLV

From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 01/14] drm/i915: Parametrize	PANEL_PORT_SELECT_VLV
Date: Tue, 19 Aug 2014 09:58:46 +0300	[thread overview]
Message-ID: <87ha19hsnt.fsf@intel.com> (raw)
In-Reply-To: <1408389369-22898-2-git-send-email-ville.syrjala@linux.intel.com>

On Mon, 18 Aug 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Passing the port as a parameter to PANEL_PORT_SELECT_VLV results in
> neater code. Sadly the PCH port select bits aren't suitable for the
> same treatment and the resulting macro would be much uglier, so
> leave those defines as is.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +--
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++--------
>  2 files changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index daac02b..9503d96 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5383,8 +5383,7 @@ enum punit_power_well {
>  #define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
>  #define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
>  #define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
> -#define  PANEL_PORT_SELECT_DPB_VLV	(1 << 30)
> -#define  PANEL_PORT_SELECT_DPC_VLV	(2 << 30)
> +#define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
>  #define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
>  #define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4f69648..43dd226 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -308,9 +308,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>  	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
>  		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
>  			PANEL_PORT_SELECT_MASK;
> -		if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
> -			return pipe;
> -		if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
> +		if (port_sel == PANEL_PORT_SELECT_VLV(port))
>  			return pipe;
>  	}
>  
> @@ -4294,6 +4292,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>  	u32 pp_on, pp_off, pp_div, port_sel = 0;
>  	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
>  	int pp_on_reg, pp_off_reg, pp_div_reg;
> +	enum port port = dp_to_dig_port(intel_dp)->port;
>  
>  	if (HAS_PCH_SPLIT(dev)) {
>  		pp_on_reg = PCH_PP_ON_DELAYS;
> @@ -4328,12 +4327,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>  	/* Haswell doesn't have any port selection bits for the panel
>  	 * power sequencer any more. */
>  	if (IS_VALLEYVIEW(dev)) {
> -		if (dp_to_dig_port(intel_dp)->port == PORT_B)
> -			port_sel = PANEL_PORT_SELECT_DPB_VLV;
> -		else
> -			port_sel = PANEL_PORT_SELECT_DPC_VLV;
> +		port_sel = PANEL_PORT_SELECT_VLV(port);
>  	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> -		if (dp_to_dig_port(intel_dp)->port == PORT_A)
> +		if (port == PORT_A)
>  			port_sel = PANEL_PORT_SELECT_DPA;
>  		else
>  			port_sel = PANEL_PORT_SELECT_DPD;
> -- 
> 1.8.5.5
>
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-- 
Jani Nikula, Intel Open Source Technology Center
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