[PATCH 0/4] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[PATCH 0/4] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[Gustavo Sousa]

Some of the parameters of used in display bandwidth calculations are
tied to the platform and are orthogonal to the display IP.  After talking
with the hardware team, we now have the information (and Bspec has been
updated) that the members deprogbwlimit and derating of struct
intel_sa_info are such platform-specific ones.

With that, we are now able to make the driver code more aligned with the
hardware by splitting structs intel_sa_info into two different structs:
one that is platform-specific and another that is display-IP-specific.

That change also allows us to simplify how we select the parameters for
the calculation.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Gustavo Sousa (4):
      drm/i915/bw: Extract platform-specific parameters
      drm/i915/bw: Deduplicate intel_sa_info instances
      drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params
      drm/i915/bw: Extract get_display_bw_params()

 drivers/gpu/drm/i915/display/intel_bw.c | 239 +++++++++++++++++++++-----------
 1 file changed, 160 insertions(+), 79 deletions(-)
---
base-commit: f074368a55893ee121ba2920497b6c25e265d190
change-id: 20260408-separate-platform-from-diplay-ip-specific-bw-params-65bfba0603be

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH 1/4] drm/i915/bw: Extract platform-specific parameters

[Gustavo Sousa]

We got confirmation from the hardware team that the bandwidth parameters
deprogbwlimit and derating are platform-specific and not tied to the
display IP.  As such, let's make sure that we use platform checks for
those.

The rest of the members of struct intel_sa_info are tied to the display
IP and we will deal with them as a follow-up.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 174 ++++++++++++++++++++++++--------
 1 file changed, 133 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 474438fc1ebc..ed840b592eff 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -375,77 +375,170 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
 	return dclk;
 }
 
+struct intel_platform_bw_params {
+	u8 deprogbwlimit;
+	u8 derating;
+};
+
+static const struct intel_platform_bw_params icl_plat_bw_params = {
+	.deprogbwlimit = 25,
+	.derating = 10,
+};
+
+static const struct intel_platform_bw_params tgl_plat_bw_params = {
+	.deprogbwlimit = 34,
+	.derating = 10,
+};
+
+static const struct intel_platform_bw_params rkl_plat_bw_params = {
+	.deprogbwlimit = 20,
+	.derating = 10,
+};
+
+static const struct intel_platform_bw_params adl_s_plat_bw_params = {
+	.deprogbwlimit = 38,
+	.derating = 10,
+};
+
+static const struct intel_platform_bw_params adl_p_plat_bw_params = {
+	.deprogbwlimit = 38,
+	.derating = 20,
+};
+
+static const struct intel_platform_bw_params bmg_plat_bw_params = {
+	.deprogbwlimit = 53,
+	.derating = 30,
+};
+
+static const struct intel_platform_bw_params bmg_ecc_plat_bw_params = {
+	.deprogbwlimit = 53,
+	.derating = 45,
+};
+
+static const struct intel_platform_bw_params ptl_plat_bw_params = {
+	.deprogbwlimit = 65,
+	.derating = 10,
+};
+
+static const struct intel_platform_bw_params wcl_plat_bw_params = {
+	.deprogbwlimit = 22,
+	.derating = 10,
+};
+
+static const struct intel_platform_bw_params *get_platform_bw_params(struct intel_display *display)
+{
+	const struct intel_platform_bw_params *ret;
+
+	if (display->platform.dgfx)
+		goto dgfx;
+
+	ret = &icl_plat_bw_params;
+	if (display->platform.icelake ||
+	    display->platform.jasperlake ||
+	    display->platform.elkhartlake)
+		return ret;
+
+	ret = &tgl_plat_bw_params;
+	if (display->platform.tigerlake)
+		return ret;
+
+	ret = &rkl_plat_bw_params;
+	if (display->platform.rocketlake)
+		return ret;
+
+	ret = &adl_s_plat_bw_params;
+	if (display->platform.alderlake_s)
+		return ret;
+
+	ret = &adl_p_plat_bw_params;
+	if (display->platform.alderlake_p)
+		return ret;
+
+	ret = &adl_s_plat_bw_params;
+	if (display->platform.meteorlake ||
+	    display->platform.lunarlake)
+		return ret;
+
+	ret = &ptl_plat_bw_params;
+	if (display->platform.pantherlake ||
+	    display->platform.novalake) {
+		if (display->platform.pantherlake_wildcatlake)
+			ret = &wcl_plat_bw_params;
+
+		return ret;
+	}
+
+	goto missing;
+
+dgfx:
+	ret = &tgl_plat_bw_params;
+	if (display->platform.dg1)
+		return ret;
+
+	ret = &bmg_plat_bw_params;
+	if (display->platform.battlemage) {
+		const struct dram_info *dram_info = intel_dram_info(display);
+
+		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
+			ret = &bmg_ecc_plat_bw_params;
+
+		return ret;
+	}
+
+missing:
+	/*
+	 * Use parameters from the most recent platform,
+	 * but raise a warning.
+	 */
+	drm_WARN(display->drm, 1,
+		 "Platform-specific bandwidth parameters not found, using possibly incompatible default values\n");
+
+	return ret;
+}
+
 struct intel_sa_info {
 	u16 displayrtids;
-	u8 deburst, deprogbwlimit, derating;
+	u8 deburst;
 };
 
 static const struct intel_sa_info icl_sa_info = {
 	.deburst = 8,
-	.deprogbwlimit = 25, /* GB/s */
 	.displayrtids = 128,
-	.derating = 10,
 };
 
 static const struct intel_sa_info tgl_sa_info = {
 	.deburst = 16,
-	.deprogbwlimit = 34, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static const struct intel_sa_info rkl_sa_info = {
 	.deburst = 8,
-	.deprogbwlimit = 20, /* GB/s */
 	.displayrtids = 128,
-	.derating = 10,
 };
 
 static const struct intel_sa_info adls_sa_info = {
 	.deburst = 16,
-	.deprogbwlimit = 38, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static const struct intel_sa_info adlp_sa_info = {
 	.deburst = 16,
-	.deprogbwlimit = 38, /* GB/s */
 	.displayrtids = 256,
-	.derating = 20,
 };
 
 static const struct intel_sa_info mtl_sa_info = {
 	.deburst = 32,
-	.deprogbwlimit = 38, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
-};
-
-static const struct intel_sa_info xe2_hpd_sa_info = {
-	.derating = 30,
-	.deprogbwlimit = 53,
-	/* Other values not used by simplified algorithm */
-};
-
-static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
-	.derating = 45,
-	.deprogbwlimit = 53,
-	/* Other values not used by simplified algorithm */
 };
 
 static const struct intel_sa_info xe3lpd_sa_info = {
 	.deburst = 32,
-	.deprogbwlimit = 65, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static const struct intel_sa_info xe3lpd_3002_sa_info = {
 	.deburst = 32,
-	.deprogbwlimit = 22, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static int icl_get_bw_info(struct intel_display *display,
@@ -453,6 +546,7 @@ static int icl_get_bw_info(struct intel_display *display,
 			   const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
+	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
 	bool is_y_tile = true; /* assume y tile may be used */
 	int num_channels = max_t(u8, 1, dram_info->num_channels);
 	int ipqdepth, ipqdepthpch = 16;
@@ -469,7 +563,7 @@ static int icl_get_bw_info(struct intel_display *display,
 	}
 
 	dclk_max = icl_sagv_max_dclk(&qi);
-	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
+	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
 	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
 	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
 
@@ -499,7 +593,7 @@ static int icl_get_bw_info(struct intel_display *display,
 			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
 
 			bi->deratedbw[j] = min(maxdebw,
-					       bw * (100 - sa->derating) / 100);
+					       bw * (100 - plat_bw_params->derating) / 100);
 
 			drm_dbg_kms(display->drm,
 				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
@@ -524,6 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 			   const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
+	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
 	bool is_y_tile = true; /* assume y tile may be used */
 	int num_channels = max_t(u8, 1, dram_info->num_channels);
 	int ipqdepth, ipqdepthpch = 16;
@@ -557,7 +652,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 	dclk_max = icl_sagv_max_dclk(&qi);
 
 	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
-	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
+	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
 
 	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
 	/*
@@ -602,7 +697,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
 
 			bi->deratedbw[j] = min(maxdebw,
-					       bw * (100 - sa->derating) / 100);
+					       bw * (100 - plat_bw_params->derating) / 100);
 			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
 							  num_channels *
 							  qi.channel_width, 8);
@@ -663,10 +758,10 @@ static void dg2_get_bw_info(struct intel_display *display)
 }
 
 static int xe2_hpd_get_bw_info(struct intel_display *display,
-			       const struct dram_info *dram_info,
-			       const struct intel_sa_info *sa)
+			       const struct dram_info *dram_info)
 {
 	struct intel_qgv_info qi = {};
+	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
 	int num_channels = dram_info->num_channels;
 	int peakbw, maxdebw;
 	int ret, i;
@@ -679,14 +774,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
 	}
 
 	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
-	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
+	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
 
 	for (i = 0; i < qi.num_points; i++) {
 		const struct intel_qgv_point *point = &qi.points[i];
 		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
 
 		display->bw.max[0].deratedbw[i] =
-			min(maxdebw, (100 - sa->derating) * bw / 100);
+			min(maxdebw, (100 - plat_bw_params->derating) * bw / 100);
 		display->bw.max[0].peakbw[i] = bw;
 
 		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
@@ -814,10 +909,7 @@ void intel_bw_init_hw(struct intel_display *display)
 		else
 			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
 	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
-		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
-			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
-		else
-			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
+		xe2_hpd_get_bw_info(display, dram_info);
 	} else if (DISPLAY_VER(display) >= 14) {
 		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
 	} else if (display->platform.dg2) {

-- 
2.53.0

Re: [PATCH 1/4] drm/i915/bw: Extract platform-specific parameters

[Jani Nikula]

On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> We got confirmation from the hardware team that the bandwidth parameters
> deprogbwlimit and derating are platform-specific and not tied to the
> display IP.  As such, let's make sure that we use platform checks for
> those.
>
> The rest of the members of struct intel_sa_info are tied to the display
> IP and we will deal with them as a follow-up.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 174 ++++++++++++++++++++++++--------
>  1 file changed, 133 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 474438fc1ebc..ed840b592eff 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -375,77 +375,170 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>  	return dclk;
>  }
>  
> +struct intel_platform_bw_params {
> +	u8 deprogbwlimit;
> +	u8 derating;
> +};
> +
> +static const struct intel_platform_bw_params icl_plat_bw_params = {
> +	.deprogbwlimit = 25,
> +	.derating = 10,
> +};
> +
> +static const struct intel_platform_bw_params tgl_plat_bw_params = {
> +	.deprogbwlimit = 34,
> +	.derating = 10,
> +};
> +
> +static const struct intel_platform_bw_params rkl_plat_bw_params = {
> +	.deprogbwlimit = 20,
> +	.derating = 10,
> +};
> +
> +static const struct intel_platform_bw_params adl_s_plat_bw_params = {
> +	.deprogbwlimit = 38,
> +	.derating = 10,
> +};
> +
> +static const struct intel_platform_bw_params adl_p_plat_bw_params = {
> +	.deprogbwlimit = 38,
> +	.derating = 20,
> +};
> +
> +static const struct intel_platform_bw_params bmg_plat_bw_params = {
> +	.deprogbwlimit = 53,
> +	.derating = 30,
> +};
> +
> +static const struct intel_platform_bw_params bmg_ecc_plat_bw_params = {
> +	.deprogbwlimit = 53,
> +	.derating = 45,
> +};
> +
> +static const struct intel_platform_bw_params ptl_plat_bw_params = {
> +	.deprogbwlimit = 65,
> +	.derating = 10,
> +};
> +
> +static const struct intel_platform_bw_params wcl_plat_bw_params = {
> +	.deprogbwlimit = 22,
> +	.derating = 10,
> +};

In the above, "plat" feels like tautology, since they're all prefixed by
platform acronyms.

> +
> +static const struct intel_platform_bw_params *get_platform_bw_params(struct intel_display *display)
> +{
> +	const struct intel_platform_bw_params *ret;
> +
> +	if (display->platform.dgfx)
> +		goto dgfx;
> +
> +	ret = &icl_plat_bw_params;
> +	if (display->platform.icelake ||
> +	    display->platform.jasperlake ||
> +	    display->platform.elkhartlake)
> +		return ret;

What's the point of assigning and returning ret?

Why not just return &icl_plat_bw_params; directly?

> +
> +	ret = &tgl_plat_bw_params;
> +	if (display->platform.tigerlake)
> +		return ret;
> +
> +	ret = &rkl_plat_bw_params;
> +	if (display->platform.rocketlake)
> +		return ret;
> +
> +	ret = &adl_s_plat_bw_params;
> +	if (display->platform.alderlake_s)
> +		return ret;
> +
> +	ret = &adl_p_plat_bw_params;
> +	if (display->platform.alderlake_p)
> +		return ret;
> +
> +	ret = &adl_s_plat_bw_params;
> +	if (display->platform.meteorlake ||
> +	    display->platform.lunarlake)
> +		return ret;
> +
> +	ret = &ptl_plat_bw_params;
> +	if (display->platform.pantherlake ||
> +	    display->platform.novalake) {
> +		if (display->platform.pantherlake_wildcatlake)
> +			ret = &wcl_plat_bw_params;
> +
> +		return ret;
> +	}
> +
> +	goto missing;
> +
> +dgfx:
> +	ret = &tgl_plat_bw_params;
> +	if (display->platform.dg1)
> +		return ret;
> +
> +	ret = &bmg_plat_bw_params;
> +	if (display->platform.battlemage) {
> +		const struct dram_info *dram_info = intel_dram_info(display);
> +
> +		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> +			ret = &bmg_ecc_plat_bw_params;
> +
> +		return ret;
> +	}
> +
> +missing:
> +	/*
> +	 * Use parameters from the most recent platform,
> +	 * but raise a warning.
> +	 */
> +	drm_WARN(display->drm, 1,
> +		 "Platform-specific bandwidth parameters not found, using possibly incompatible default values\n");
> +
> +	return ret;

I don't understand at all why the function is written the way it
is. Seems like it should be a regular if-ladder like we have, with zero
gotos.

> +}
> +
>  struct intel_sa_info {
>  	u16 displayrtids;
> -	u8 deburst, deprogbwlimit, derating;
> +	u8 deburst;
>  };
>  
>  static const struct intel_sa_info icl_sa_info = {
>  	.deburst = 8,
> -	.deprogbwlimit = 25, /* GB/s */
>  	.displayrtids = 128,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info tgl_sa_info = {
>  	.deburst = 16,
> -	.deprogbwlimit = 34, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info rkl_sa_info = {
>  	.deburst = 8,
> -	.deprogbwlimit = 20, /* GB/s */
>  	.displayrtids = 128,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info adls_sa_info = {
>  	.deburst = 16,
> -	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info adlp_sa_info = {
>  	.deburst = 16,
> -	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 20,
>  };
>  
>  static const struct intel_sa_info mtl_sa_info = {
>  	.deburst = 32,
> -	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
> -};
> -
> -static const struct intel_sa_info xe2_hpd_sa_info = {
> -	.derating = 30,
> -	.deprogbwlimit = 53,
> -	/* Other values not used by simplified algorithm */
> -};
> -
> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
> -	.derating = 45,
> -	.deprogbwlimit = 53,
> -	/* Other values not used by simplified algorithm */
>  };
>  
>  static const struct intel_sa_info xe3lpd_sa_info = {
>  	.deburst = 32,
> -	.deprogbwlimit = 65, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>  	.deburst = 32,
> -	.deprogbwlimit = 22, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static int icl_get_bw_info(struct intel_display *display,
> @@ -453,6 +546,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  			   const struct intel_sa_info *sa)
>  {
>  	struct intel_qgv_info qi = {};
> +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);

Perhaps it would be better to pass this in instead of every function
having the call.

Nitpick, "plat" is not an abbreviation I'm fond of.

>  	bool is_y_tile = true; /* assume y tile may be used */
>  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>  	int ipqdepth, ipqdepthpch = 16;
> @@ -469,7 +563,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  	}
>  
>  	dclk_max = icl_sagv_max_dclk(&qi);
> -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>  
> @@ -499,7 +593,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>  
>  			bi->deratedbw[j] = min(maxdebw,
> -					       bw * (100 - sa->derating) / 100);
> +					       bw * (100 - plat_bw_params->derating) / 100);
>  
>  			drm_dbg_kms(display->drm,
>  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> @@ -524,6 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  			   const struct intel_sa_info *sa)
>  {
>  	struct intel_qgv_info qi = {};
> +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>  	bool is_y_tile = true; /* assume y tile may be used */
>  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>  	int ipqdepth, ipqdepthpch = 16;
> @@ -557,7 +652,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  	dclk_max = icl_sagv_max_dclk(&qi);
>  
>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>  
>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>  	/*
> @@ -602,7 +697,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>  
>  			bi->deratedbw[j] = min(maxdebw,
> -					       bw * (100 - sa->derating) / 100);
> +					       bw * (100 - plat_bw_params->derating) / 100);
>  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>  							  num_channels *
>  							  qi.channel_width, 8);
> @@ -663,10 +758,10 @@ static void dg2_get_bw_info(struct intel_display *display)
>  }
>  
>  static int xe2_hpd_get_bw_info(struct intel_display *display,
> -			       const struct dram_info *dram_info,
> -			       const struct intel_sa_info *sa)
> +			       const struct dram_info *dram_info)
>  {
>  	struct intel_qgv_info qi = {};
> +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>  	int num_channels = dram_info->num_channels;
>  	int peakbw, maxdebw;
>  	int ret, i;
> @@ -679,14 +774,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>  	}
>  
>  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
> +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>  
>  	for (i = 0; i < qi.num_points; i++) {
>  		const struct intel_qgv_point *point = &qi.points[i];
>  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>  
>  		display->bw.max[0].deratedbw[i] =
> -			min(maxdebw, (100 - sa->derating) * bw / 100);
> +			min(maxdebw, (100 - plat_bw_params->derating) * bw / 100);
>  		display->bw.max[0].peakbw[i] = bw;
>  
>  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
> @@ -814,10 +909,7 @@ void intel_bw_init_hw(struct intel_display *display)
>  		else
>  			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
> -		else
> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
> +		xe2_hpd_get_bw_info(display, dram_info);
>  	} else if (DISPLAY_VER(display) >= 14) {
>  		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>  	} else if (display->platform.dg2) {

-- 
Jani Nikula, Intel

Re: [PATCH 1/4] drm/i915/bw: Extract platform-specific parameters

[Gustavo Sousa]

Jani Nikula <jani.nikula@linux.intel.com> writes:

> On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> We got confirmation from the hardware team that the bandwidth parameters
>> deprogbwlimit and derating are platform-specific and not tied to the
>> display IP.  As such, let's make sure that we use platform checks for
>> those.
>>
>> The rest of the members of struct intel_sa_info are tied to the display
>> IP and we will deal with them as a follow-up.
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 174 ++++++++++++++++++++++++--------
>>  1 file changed, 133 insertions(+), 41 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index 474438fc1ebc..ed840b592eff 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -375,77 +375,170 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>>  	return dclk;
>>  }
>>  
>> +struct intel_platform_bw_params {
>> +	u8 deprogbwlimit;
>> +	u8 derating;
>> +};
>> +
>> +static const struct intel_platform_bw_params icl_plat_bw_params = {
>> +	.deprogbwlimit = 25,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_platform_bw_params tgl_plat_bw_params = {
>> +	.deprogbwlimit = 34,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_platform_bw_params rkl_plat_bw_params = {
>> +	.deprogbwlimit = 20,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_platform_bw_params adl_s_plat_bw_params = {
>> +	.deprogbwlimit = 38,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_platform_bw_params adl_p_plat_bw_params = {
>> +	.deprogbwlimit = 38,
>> +	.derating = 20,
>> +};
>> +
>> +static const struct intel_platform_bw_params bmg_plat_bw_params = {
>> +	.deprogbwlimit = 53,
>> +	.derating = 30,
>> +};
>> +
>> +static const struct intel_platform_bw_params bmg_ecc_plat_bw_params = {
>> +	.deprogbwlimit = 53,
>> +	.derating = 45,
>> +};
>> +
>> +static const struct intel_platform_bw_params ptl_plat_bw_params = {
>> +	.deprogbwlimit = 65,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_platform_bw_params wcl_plat_bw_params = {
>> +	.deprogbwlimit = 22,
>> +	.derating = 10,
>> +};
>
> In the above, "plat" feels like tautology, since they're all prefixed by
> platform acronyms.

Yeah, true.  In an upcoming patch I also introduce display-IP-specific
structs, and I decided to use plat vs disp to differentiate
(e.g. tgl_plat_bw_params vs tgl_disp_bw_params).

Any suggestion of how to make it better?

>
>> +
>> +static const struct intel_platform_bw_params *get_platform_bw_params(struct intel_display *display)
>> +{
>> +	const struct intel_platform_bw_params *ret;
>> +
>> +	if (display->platform.dgfx)
>> +		goto dgfx;
>> +
>> +	ret = &icl_plat_bw_params;
>> +	if (display->platform.icelake ||
>> +	    display->platform.jasperlake ||
>> +	    display->platform.elkhartlake)
>> +		return ret;
>
> What's the point of assigning and returning ret?
>
> Why not just return &icl_plat_bw_params; directly?

I would like that we always have a default to be returned if somehow we
miss adding a new case for a new platform (hence the "missing:"
label).  The idea of assigning to ret is for it to have a valid value
when hitting the missing: point.

Arguably we could also only use this pattern only in the last case, but that
would feel like an inconsistency and prone to someone forgetting to
"push" it to the next new platform when the time comes.

I would be much happier with a switch-case statement that would have a
"default:" combined with "fallthrough", but I think that's not possible
with the current way we handle platform matching in the display code.

>
>> +
>> +	ret = &tgl_plat_bw_params;
>> +	if (display->platform.tigerlake)
>> +		return ret;
>> +
>> +	ret = &rkl_plat_bw_params;
>> +	if (display->platform.rocketlake)
>> +		return ret;
>> +
>> +	ret = &adl_s_plat_bw_params;
>> +	if (display->platform.alderlake_s)
>> +		return ret;
>> +
>> +	ret = &adl_p_plat_bw_params;
>> +	if (display->platform.alderlake_p)
>> +		return ret;
>> +
>> +	ret = &adl_s_plat_bw_params;
>> +	if (display->platform.meteorlake ||
>> +	    display->platform.lunarlake)
>> +		return ret;
>> +
>> +	ret = &ptl_plat_bw_params;
>> +	if (display->platform.pantherlake ||
>> +	    display->platform.novalake) {
>> +		if (display->platform.pantherlake_wildcatlake)
>> +			ret = &wcl_plat_bw_params;
>> +
>> +		return ret;
>> +	}
>> +
>> +	goto missing;
>> +
>> +dgfx:
>> +	ret = &tgl_plat_bw_params;
>> +	if (display->platform.dg1)
>> +		return ret;
>> +
>> +	ret = &bmg_plat_bw_params;
>> +	if (display->platform.battlemage) {
>> +		const struct dram_info *dram_info = intel_dram_info(display);
>> +
>> +		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> +			ret = &bmg_ecc_plat_bw_params;
>> +
>> +		return ret;
>> +	}
>> +
>> +missing:
>> +	/*
>> +	 * Use parameters from the most recent platform,
>> +	 * but raise a warning.
>> +	 */
>> +	drm_WARN(display->drm, 1,
>> +		 "Platform-specific bandwidth parameters not found, using possibly incompatible default values\n");
>> +
>> +	return ret;
>
> I don't understand at all why the function is written the way it
> is. Seems like it should be a regular if-ladder like we have, with zero
> gotos.

Just wanted the default for the missing case to be the most recent
platform in an "automated" way, with separate ordering for dgfx and
integrated.

Do you suggest we do not have such a default and cause a null-pointer
deref (on purpose) if we forget to add a new platform?

Or always "manually" update the default when we add a new
platform-specific instance?

>
>> +}
>> +
>>  struct intel_sa_info {
>>  	u16 displayrtids;
>> -	u8 deburst, deprogbwlimit, derating;
>> +	u8 deburst;
>>  };
>>  
>>  static const struct intel_sa_info icl_sa_info = {
>>  	.deburst = 8,
>> -	.deprogbwlimit = 25, /* GB/s */
>>  	.displayrtids = 128,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info tgl_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 34, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info rkl_sa_info = {
>>  	.deburst = 8,
>> -	.deprogbwlimit = 20, /* GB/s */
>>  	.displayrtids = 128,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info adls_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info adlp_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 20,
>>  };
>>  
>>  static const struct intel_sa_info mtl_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_sa_info = {
>> -	.derating = 30,
>> -	.deprogbwlimit = 53,
>> -	/* Other values not used by simplified algorithm */
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>> -	.derating = 45,
>> -	.deprogbwlimit = 53,
>> -	/* Other values not used by simplified algorithm */
>>  };
>>  
>>  static const struct intel_sa_info xe3lpd_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 65, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 22, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static int icl_get_bw_info(struct intel_display *display,
>> @@ -453,6 +546,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  			   const struct intel_sa_info *sa)
>>  {
>>  	struct intel_qgv_info qi = {};
>> +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>
> Perhaps it would be better to pass this in instead of every function
> having the call.

Okay. I think I'll have to rework patch #4 as well
then :-)

>
> Nitpick, "plat" is not an abbreviation I'm fond of.

Noted. 

Out of curiosity: because it is a noun of its own? Or is it something
else?

--
Gustavo Sousa

>
>>  	bool is_y_tile = true; /* assume y tile may be used */
>>  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>>  	int ipqdepth, ipqdepthpch = 16;
>> @@ -469,7 +563,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  	}
>>  
>>  	dclk_max = icl_sagv_max_dclk(&qi);
>> -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>>  
>> @@ -499,7 +593,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>  
>>  			bi->deratedbw[j] = min(maxdebw,
>> -					       bw * (100 - sa->derating) / 100);
>> +					       bw * (100 - plat_bw_params->derating) / 100);
>>  
>>  			drm_dbg_kms(display->drm,
>>  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>> @@ -524,6 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  			   const struct intel_sa_info *sa)
>>  {
>>  	struct intel_qgv_info qi = {};
>> +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>>  	bool is_y_tile = true; /* assume y tile may be used */
>>  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>>  	int ipqdepth, ipqdepthpch = 16;
>> @@ -557,7 +652,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  	dclk_max = icl_sagv_max_dclk(&qi);
>>  
>>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>  
>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>  	/*
>> @@ -602,7 +697,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>  
>>  			bi->deratedbw[j] = min(maxdebw,
>> -					       bw * (100 - sa->derating) / 100);
>> +					       bw * (100 - plat_bw_params->derating) / 100);
>>  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>>  							  num_channels *
>>  							  qi.channel_width, 8);
>> @@ -663,10 +758,10 @@ static void dg2_get_bw_info(struct intel_display *display)
>>  }
>>  
>>  static int xe2_hpd_get_bw_info(struct intel_display *display,
>> -			       const struct dram_info *dram_info,
>> -			       const struct intel_sa_info *sa)
>> +			       const struct dram_info *dram_info)
>>  {
>>  	struct intel_qgv_info qi = {};
>> +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>>  	int num_channels = dram_info->num_channels;
>>  	int peakbw, maxdebw;
>>  	int ret, i;
>> @@ -679,14 +774,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>>  	}
>>  
>>  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>  
>>  	for (i = 0; i < qi.num_points; i++) {
>>  		const struct intel_qgv_point *point = &qi.points[i];
>>  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>>  
>>  		display->bw.max[0].deratedbw[i] =
>> -			min(maxdebw, (100 - sa->derating) * bw / 100);
>> +			min(maxdebw, (100 - plat_bw_params->derating) * bw / 100);
>>  		display->bw.max[0].peakbw[i] = bw;
>>  
>>  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>> @@ -814,10 +909,7 @@ void intel_bw_init_hw(struct intel_display *display)
>>  		else
>>  			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>>  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>> -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>> -		else
>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>> +		xe2_hpd_get_bw_info(display, dram_info);
>>  	} else if (DISPLAY_VER(display) >= 14) {
>>  		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>>  	} else if (display->platform.dg2) {
>
> -- 
> Jani Nikula, Intel

Re: [PATCH 1/4] drm/i915/bw: Extract platform-specific parameters

[Matt Roper]

On Wed, Apr 08, 2026 at 10:16:42PM +0300, Jani Nikula wrote:
> On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> > We got confirmation from the hardware team that the bandwidth parameters
> > deprogbwlimit and derating are platform-specific and not tied to the
> > display IP.  As such, let's make sure that we use platform checks for
> > those.
> >
> > The rest of the members of struct intel_sa_info are tied to the display
> > IP and we will deal with them as a follow-up.
> >
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c | 174 ++++++++++++++++++++++++--------
> >  1 file changed, 133 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 474438fc1ebc..ed840b592eff 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -375,77 +375,170 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
> >  	return dclk;
> >  }
> >  
> > +struct intel_platform_bw_params {
> > +	u8 deprogbwlimit;
> > +	u8 derating;
> > +};
> > +
> > +static const struct intel_platform_bw_params icl_plat_bw_params = {
> > +	.deprogbwlimit = 25,
> > +	.derating = 10,
> > +};
> > +
> > +static const struct intel_platform_bw_params tgl_plat_bw_params = {
> > +	.deprogbwlimit = 34,
> > +	.derating = 10,
> > +};
> > +
> > +static const struct intel_platform_bw_params rkl_plat_bw_params = {
> > +	.deprogbwlimit = 20,
> > +	.derating = 10,
> > +};
> > +
> > +static const struct intel_platform_bw_params adl_s_plat_bw_params = {
> > +	.deprogbwlimit = 38,
> > +	.derating = 10,
> > +};
> > +
> > +static const struct intel_platform_bw_params adl_p_plat_bw_params = {
> > +	.deprogbwlimit = 38,
> > +	.derating = 20,
> > +};
> > +
> > +static const struct intel_platform_bw_params bmg_plat_bw_params = {
> > +	.deprogbwlimit = 53,
> > +	.derating = 30,
> > +};
> > +
> > +static const struct intel_platform_bw_params bmg_ecc_plat_bw_params = {
> > +	.deprogbwlimit = 53,
> > +	.derating = 45,
> > +};
> > +
> > +static const struct intel_platform_bw_params ptl_plat_bw_params = {
> > +	.deprogbwlimit = 65,
> > +	.derating = 10,
> > +};
> > +
> > +static const struct intel_platform_bw_params wcl_plat_bw_params = {
> > +	.deprogbwlimit = 22,
> > +	.derating = 10,
> > +};
> 
> In the above, "plat" feels like tautology, since they're all prefixed by
> platform acronyms.

"soc" might be more consistent with what we (and various hardware docs)
do to refer to "stuff that's outside the graphics/media/display IP and
doesn't relate to GMD_ID version numbers."  Technically "soc" is a bit
of a misnomer too since a lot of our recent platforms are multi-chip and
not truly SoC's anymore, but the intent is still understandable.

> 
> > +
> > +static const struct intel_platform_bw_params *get_platform_bw_params(struct intel_display *display)
> > +{
> > +	const struct intel_platform_bw_params *ret;
> > +
> > +	if (display->platform.dgfx)
> > +		goto dgfx;
> > +
> > +	ret = &icl_plat_bw_params;
> > +	if (display->platform.icelake ||
> > +	    display->platform.jasperlake ||
> > +	    display->platform.elkhartlake)
> > +		return ret;
> 
> What's the point of assigning and returning ret?
> 
> Why not just return &icl_plat_bw_params; directly?
> 

It looks like the intent might have been to let people keep copy/pasting
the same pattern and have the fallback at the end always default back to
whatever the "newest" one was if a proper match wasn't found.  But I
agree that the handling here feels awkward and a simple if/else ladder
would be preferable.


Matt

> > +
> > +	ret = &tgl_plat_bw_params;
> > +	if (display->platform.tigerlake)
> > +		return ret;
> > +
> > +	ret = &rkl_plat_bw_params;
> > +	if (display->platform.rocketlake)
> > +		return ret;
> > +
> > +	ret = &adl_s_plat_bw_params;
> > +	if (display->platform.alderlake_s)
> > +		return ret;
> > +
> > +	ret = &adl_p_plat_bw_params;
> > +	if (display->platform.alderlake_p)
> > +		return ret;
> > +
> > +	ret = &adl_s_plat_bw_params;
> > +	if (display->platform.meteorlake ||
> > +	    display->platform.lunarlake)
> > +		return ret;
> > +
> > +	ret = &ptl_plat_bw_params;
> > +	if (display->platform.pantherlake ||
> > +	    display->platform.novalake) {
> > +		if (display->platform.pantherlake_wildcatlake)
> > +			ret = &wcl_plat_bw_params;
> > +
> > +		return ret;
> > +	}
> > +
> > +	goto missing;
> > +
> > +dgfx:
> > +	ret = &tgl_plat_bw_params;
> > +	if (display->platform.dg1)
> > +		return ret;
> > +
> > +	ret = &bmg_plat_bw_params;
> > +	if (display->platform.battlemage) {
> > +		const struct dram_info *dram_info = intel_dram_info(display);
> > +
> > +		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> > +			ret = &bmg_ecc_plat_bw_params;
> > +
> > +		return ret;
> > +	}
> > +
> > +missing:
> > +	/*
> > +	 * Use parameters from the most recent platform,
> > +	 * but raise a warning.
> > +	 */
> > +	drm_WARN(display->drm, 1,
> > +		 "Platform-specific bandwidth parameters not found, using possibly incompatible default values\n");
> > +
> > +	return ret;
> 
> I don't understand at all why the function is written the way it
> is. Seems like it should be a regular if-ladder like we have, with zero
> gotos.
> 
> > +}
> > +
> >  struct intel_sa_info {
> >  	u16 displayrtids;
> > -	u8 deburst, deprogbwlimit, derating;
> > +	u8 deburst;
> >  };
> >  
> >  static const struct intel_sa_info icl_sa_info = {
> >  	.deburst = 8,
> > -	.deprogbwlimit = 25, /* GB/s */
> >  	.displayrtids = 128,
> > -	.derating = 10,
> >  };
> >  
> >  static const struct intel_sa_info tgl_sa_info = {
> >  	.deburst = 16,
> > -	.deprogbwlimit = 34, /* GB/s */
> >  	.displayrtids = 256,
> > -	.derating = 10,
> >  };
> >  
> >  static const struct intel_sa_info rkl_sa_info = {
> >  	.deburst = 8,
> > -	.deprogbwlimit = 20, /* GB/s */
> >  	.displayrtids = 128,
> > -	.derating = 10,
> >  };
> >  
> >  static const struct intel_sa_info adls_sa_info = {
> >  	.deburst = 16,
> > -	.deprogbwlimit = 38, /* GB/s */
> >  	.displayrtids = 256,
> > -	.derating = 10,
> >  };
> >  
> >  static const struct intel_sa_info adlp_sa_info = {
> >  	.deburst = 16,
> > -	.deprogbwlimit = 38, /* GB/s */
> >  	.displayrtids = 256,
> > -	.derating = 20,
> >  };
> >  
> >  static const struct intel_sa_info mtl_sa_info = {
> >  	.deburst = 32,
> > -	.deprogbwlimit = 38, /* GB/s */
> >  	.displayrtids = 256,
> > -	.derating = 10,
> > -};
> > -
> > -static const struct intel_sa_info xe2_hpd_sa_info = {
> > -	.derating = 30,
> > -	.deprogbwlimit = 53,
> > -	/* Other values not used by simplified algorithm */
> > -};
> > -
> > -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
> > -	.derating = 45,
> > -	.deprogbwlimit = 53,
> > -	/* Other values not used by simplified algorithm */
> >  };
> >  
> >  static const struct intel_sa_info xe3lpd_sa_info = {
> >  	.deburst = 32,
> > -	.deprogbwlimit = 65, /* GB/s */
> >  	.displayrtids = 256,
> > -	.derating = 10,
> >  };
> >  
> >  static const struct intel_sa_info xe3lpd_3002_sa_info = {
> >  	.deburst = 32,
> > -	.deprogbwlimit = 22, /* GB/s */
> >  	.displayrtids = 256,
> > -	.derating = 10,
> >  };
> >  
> >  static int icl_get_bw_info(struct intel_display *display,
> > @@ -453,6 +546,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >  			   const struct intel_sa_info *sa)
> >  {
> >  	struct intel_qgv_info qi = {};
> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> 
> Perhaps it would be better to pass this in instead of every function
> having the call.
> 
> Nitpick, "plat" is not an abbreviation I'm fond of.
> 
> >  	bool is_y_tile = true; /* assume y tile may be used */
> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
> >  	int ipqdepth, ipqdepthpch = 16;
> > @@ -469,7 +563,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >  	}
> >  
> >  	dclk_max = icl_sagv_max_dclk(&qi);
> > -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> >  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
> >  
> > @@ -499,7 +593,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
> >  
> >  			bi->deratedbw[j] = min(maxdebw,
> > -					       bw * (100 - sa->derating) / 100);
> > +					       bw * (100 - plat_bw_params->derating) / 100);
> >  
> >  			drm_dbg_kms(display->drm,
> >  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> > @@ -524,6 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >  			   const struct intel_sa_info *sa)
> >  {
> >  	struct intel_qgv_info qi = {};
> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> >  	bool is_y_tile = true; /* assume y tile may be used */
> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
> >  	int ipqdepth, ipqdepthpch = 16;
> > @@ -557,7 +652,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >  	dclk_max = icl_sagv_max_dclk(&qi);
> >  
> >  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> >  
> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> >  	/*
> > @@ -602,7 +697,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
> >  
> >  			bi->deratedbw[j] = min(maxdebw,
> > -					       bw * (100 - sa->derating) / 100);
> > +					       bw * (100 - plat_bw_params->derating) / 100);
> >  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
> >  							  num_channels *
> >  							  qi.channel_width, 8);
> > @@ -663,10 +758,10 @@ static void dg2_get_bw_info(struct intel_display *display)
> >  }
> >  
> >  static int xe2_hpd_get_bw_info(struct intel_display *display,
> > -			       const struct dram_info *dram_info,
> > -			       const struct intel_sa_info *sa)
> > +			       const struct dram_info *dram_info)
> >  {
> >  	struct intel_qgv_info qi = {};
> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> >  	int num_channels = dram_info->num_channels;
> >  	int peakbw, maxdebw;
> >  	int ret, i;
> > @@ -679,14 +774,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
> >  	}
> >  
> >  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
> >  
> >  	for (i = 0; i < qi.num_points; i++) {
> >  		const struct intel_qgv_point *point = &qi.points[i];
> >  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
> >  
> >  		display->bw.max[0].deratedbw[i] =
> > -			min(maxdebw, (100 - sa->derating) * bw / 100);
> > +			min(maxdebw, (100 - plat_bw_params->derating) * bw / 100);
> >  		display->bw.max[0].peakbw[i] = bw;
> >  
> >  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
> > @@ -814,10 +909,7 @@ void intel_bw_init_hw(struct intel_display *display)
> >  		else
> >  			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> >  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> > -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
> > -		else
> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
> > +		xe2_hpd_get_bw_info(display, dram_info);
> >  	} else if (DISPLAY_VER(display) >= 14) {
> >  		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
> >  	} else if (display->platform.dg2) {
> 
> -- 
> Jani Nikula, Intel

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 1/4] drm/i915/bw: Extract platform-specific parameters

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Wed, Apr 08, 2026 at 10:16:42PM +0300, Jani Nikula wrote:
>> On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> > We got confirmation from the hardware team that the bandwidth parameters
>> > deprogbwlimit and derating are platform-specific and not tied to the
>> > display IP.  As such, let's make sure that we use platform checks for
>> > those.
>> >
>> > The rest of the members of struct intel_sa_info are tied to the display
>> > IP and we will deal with them as a follow-up.
>> >
>> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_bw.c | 174 ++++++++++++++++++++++++--------
>> >  1 file changed, 133 insertions(+), 41 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> > index 474438fc1ebc..ed840b592eff 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> > @@ -375,77 +375,170 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>> >  	return dclk;
>> >  }
>> >  
>> > +struct intel_platform_bw_params {
>> > +	u8 deprogbwlimit;
>> > +	u8 derating;
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params icl_plat_bw_params = {
>> > +	.deprogbwlimit = 25,
>> > +	.derating = 10,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params tgl_plat_bw_params = {
>> > +	.deprogbwlimit = 34,
>> > +	.derating = 10,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params rkl_plat_bw_params = {
>> > +	.deprogbwlimit = 20,
>> > +	.derating = 10,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params adl_s_plat_bw_params = {
>> > +	.deprogbwlimit = 38,
>> > +	.derating = 10,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params adl_p_plat_bw_params = {
>> > +	.deprogbwlimit = 38,
>> > +	.derating = 20,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params bmg_plat_bw_params = {
>> > +	.deprogbwlimit = 53,
>> > +	.derating = 30,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params bmg_ecc_plat_bw_params = {
>> > +	.deprogbwlimit = 53,
>> > +	.derating = 45,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params ptl_plat_bw_params = {
>> > +	.deprogbwlimit = 65,
>> > +	.derating = 10,
>> > +};
>> > +
>> > +static const struct intel_platform_bw_params wcl_plat_bw_params = {
>> > +	.deprogbwlimit = 22,
>> > +	.derating = 10,
>> > +};
>> 
>> In the above, "plat" feels like tautology, since they're all prefixed by
>> platform acronyms.
>
> "soc" might be more consistent with what we (and various hardware docs)
> do to refer to "stuff that's outside the graphics/media/display IP and
> doesn't relate to GMD_ID version numbers."  Technically "soc" is a bit
> of a misnomer too since a lot of our recent platforms are multi-chip and
> not truly SoC's anymore, but the intent is still understandable.

Yeah. I intetionally prefered to use "platform" as a general term to
refer to either SoC or multi-chip package.  Do you prefer that we name
the struct type intel_soc_bw_params?

What about intel_display_bw_params that is added later? Is that a good
name? I thought intel_ip_bw_params would be a bit vague, since we have
different types of IPs (display being one of them) in the platform.

>
>> 
>> > +
>> > +static const struct intel_platform_bw_params *get_platform_bw_params(struct intel_display *display)
>> > +{
>> > +	const struct intel_platform_bw_params *ret;
>> > +
>> > +	if (display->platform.dgfx)
>> > +		goto dgfx;
>> > +
>> > +	ret = &icl_plat_bw_params;
>> > +	if (display->platform.icelake ||
>> > +	    display->platform.jasperlake ||
>> > +	    display->platform.elkhartlake)
>> > +		return ret;
>> 
>> What's the point of assigning and returning ret?
>> 
>> Why not just return &icl_plat_bw_params; directly?
>> 
>
> It looks like the intent might have been to let people keep copy/pasting
> the same pattern and have the fallback at the end always default back to
> whatever the "newest" one was if a proper match wasn't found.  But I
> agree that the handling here feels awkward and a simple if/else ladder
> would be preferable.

Yeah, allowing developers to easily add new platforms without too much
churn was the intention here.  I knew this style was unconventional, but
I thought the intent justified it (and IMO the code is still readable,
although admittedly a bit weird).

If that's not acceptable, would something along the lines of below be
accepted?

    if (display->platformOB.dgfx) {
        if (...)
             return platform_a_params;
        else if (...)
             return platform_b_params;
        else if (...)
             return platform_c_params;
        
        default_params = platform_c_params;
    } else {
        if (...)
             return platform_d_params;
        else if (...)
             return platform_e_params;
        else if (...)
             return platform_f_params;
        
        default_params = platform_f_params;
    }
    
    do_warning();
    return default_params;
--
Gustavo Sousa

>
>
> Matt
>
>> > +
>> > +	ret = &tgl_plat_bw_params;
>> > +	if (display->platform.tigerlake)
>> > +		return ret;
>> > +
>> > +	ret = &rkl_plat_bw_params;
>> > +	if (display->platform.rocketlake)
>> > +		return ret;
>> > +
>> > +	ret = &adl_s_plat_bw_params;
>> > +	if (display->platform.alderlake_s)
>> > +		return ret;
>> > +
>> > +	ret = &adl_p_plat_bw_params;
>> > +	if (display->platform.alderlake_p)
>> > +		return ret;
>> > +
>> > +	ret = &adl_s_plat_bw_params;
>> > +	if (display->platform.meteorlake ||
>> > +	    display->platform.lunarlake)
>> > +		return ret;
>> > +
>> > +	ret = &ptl_plat_bw_params;
>> > +	if (display->platform.pantherlake ||
>> > +	    display->platform.novalake) {
>> > +		if (display->platform.pantherlake_wildcatlake)
>> > +			ret = &wcl_plat_bw_params;
>> > +
>> > +		return ret;
>> > +	}
>> > +
>> > +	goto missing;
>> > +
>> > +dgfx:
>> > +	ret = &tgl_plat_bw_params;
>> > +	if (display->platform.dg1)
>> > +		return ret;
>> > +
>> > +	ret = &bmg_plat_bw_params;
>> > +	if (display->platform.battlemage) {
>> > +		const struct dram_info *dram_info = intel_dram_info(display);
>> > +
>> > +		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> > +			ret = &bmg_ecc_plat_bw_params;
>> > +
>> > +		return ret;
>> > +	}
>> > +
>> > +missing:
>> > +	/*
>> > +	 * Use parameters from the most recent platform,
>> > +	 * but raise a warning.
>> > +	 */
>> > +	drm_WARN(display->drm, 1,
>> > +		 "Platform-specific bandwidth parameters not found, using possibly incompatible default values\n");
>> > +
>> > +	return ret;
>> 
>> I don't understand at all why the function is written the way it
>> is. Seems like it should be a regular if-ladder like we have, with zero
>> gotos.
>> 
>> > +}
>> > +
>> >  struct intel_sa_info {
>> >  	u16 displayrtids;
>> > -	u8 deburst, deprogbwlimit, derating;
>> > +	u8 deburst;
>> >  };
>> >  
>> >  static const struct intel_sa_info icl_sa_info = {
>> >  	.deburst = 8,
>> > -	.deprogbwlimit = 25, /* GB/s */
>> >  	.displayrtids = 128,
>> > -	.derating = 10,
>> >  };
>> >  
>> >  static const struct intel_sa_info tgl_sa_info = {
>> >  	.deburst = 16,
>> > -	.deprogbwlimit = 34, /* GB/s */
>> >  	.displayrtids = 256,
>> > -	.derating = 10,
>> >  };
>> >  
>> >  static const struct intel_sa_info rkl_sa_info = {
>> >  	.deburst = 8,
>> > -	.deprogbwlimit = 20, /* GB/s */
>> >  	.displayrtids = 128,
>> > -	.derating = 10,
>> >  };
>> >  
>> >  static const struct intel_sa_info adls_sa_info = {
>> >  	.deburst = 16,
>> > -	.deprogbwlimit = 38, /* GB/s */
>> >  	.displayrtids = 256,
>> > -	.derating = 10,
>> >  };
>> >  
>> >  static const struct intel_sa_info adlp_sa_info = {
>> >  	.deburst = 16,
>> > -	.deprogbwlimit = 38, /* GB/s */
>> >  	.displayrtids = 256,
>> > -	.derating = 20,
>> >  };
>> >  
>> >  static const struct intel_sa_info mtl_sa_info = {
>> >  	.deburst = 32,
>> > -	.deprogbwlimit = 38, /* GB/s */
>> >  	.displayrtids = 256,
>> > -	.derating = 10,
>> > -};
>> > -
>> > -static const struct intel_sa_info xe2_hpd_sa_info = {
>> > -	.derating = 30,
>> > -	.deprogbwlimit = 53,
>> > -	/* Other values not used by simplified algorithm */
>> > -};
>> > -
>> > -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>> > -	.derating = 45,
>> > -	.deprogbwlimit = 53,
>> > -	/* Other values not used by simplified algorithm */
>> >  };
>> >  
>> >  static const struct intel_sa_info xe3lpd_sa_info = {
>> >  	.deburst = 32,
>> > -	.deprogbwlimit = 65, /* GB/s */
>> >  	.displayrtids = 256,
>> > -	.derating = 10,
>> >  };
>> >  
>> >  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>> >  	.deburst = 32,
>> > -	.deprogbwlimit = 22, /* GB/s */
>> >  	.displayrtids = 256,
>> > -	.derating = 10,
>> >  };
>> >  
>> >  static int icl_get_bw_info(struct intel_display *display,
>> > @@ -453,6 +546,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> >  			   const struct intel_sa_info *sa)
>> >  {
>> >  	struct intel_qgv_info qi = {};
>> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> 
>> Perhaps it would be better to pass this in instead of every function
>> having the call.
>> 
>> Nitpick, "plat" is not an abbreviation I'm fond of.
>> 
>> >  	bool is_y_tile = true; /* assume y tile may be used */
>> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>> >  	int ipqdepth, ipqdepthpch = 16;
>> > @@ -469,7 +563,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> >  	}
>> >  
>> >  	dclk_max = icl_sagv_max_dclk(&qi);
>> > -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> >  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>> >  
>> > @@ -499,7 +593,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>> >  
>> >  			bi->deratedbw[j] = min(maxdebw,
>> > -					       bw * (100 - sa->derating) / 100);
>> > +					       bw * (100 - plat_bw_params->derating) / 100);
>> >  
>> >  			drm_dbg_kms(display->drm,
>> >  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>> > @@ -524,6 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> >  			   const struct intel_sa_info *sa)
>> >  {
>> >  	struct intel_qgv_info qi = {};
>> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> >  	bool is_y_tile = true; /* assume y tile may be used */
>> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>> >  	int ipqdepth, ipqdepthpch = 16;
>> > @@ -557,7 +652,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> >  	dclk_max = icl_sagv_max_dclk(&qi);
>> >  
>> >  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> >  
>> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> >  	/*
>> > @@ -602,7 +697,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>> >  
>> >  			bi->deratedbw[j] = min(maxdebw,
>> > -					       bw * (100 - sa->derating) / 100);
>> > +					       bw * (100 - plat_bw_params->derating) / 100);
>> >  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>> >  							  num_channels *
>> >  							  qi.channel_width, 8);
>> > @@ -663,10 +758,10 @@ static void dg2_get_bw_info(struct intel_display *display)
>> >  }
>> >  
>> >  static int xe2_hpd_get_bw_info(struct intel_display *display,
>> > -			       const struct dram_info *dram_info,
>> > -			       const struct intel_sa_info *sa)
>> > +			       const struct dram_info *dram_info)
>> >  {
>> >  	struct intel_qgv_info qi = {};
>> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> >  	int num_channels = dram_info->num_channels;
>> >  	int peakbw, maxdebw;
>> >  	int ret, i;
>> > @@ -679,14 +774,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>> >  	}
>> >  
>> >  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> >  
>> >  	for (i = 0; i < qi.num_points; i++) {
>> >  		const struct intel_qgv_point *point = &qi.points[i];
>> >  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>> >  
>> >  		display->bw.max[0].deratedbw[i] =
>> > -			min(maxdebw, (100 - sa->derating) * bw / 100);
>> > +			min(maxdebw, (100 - plat_bw_params->derating) * bw / 100);
>> >  		display->bw.max[0].peakbw[i] = bw;
>> >  
>> >  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>> > @@ -814,10 +909,7 @@ void intel_bw_init_hw(struct intel_display *display)
>> >  		else
>> >  			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> >  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>> > -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>> > -		else
>> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>> > +		xe2_hpd_get_bw_info(display, dram_info);
>> >  	} else if (DISPLAY_VER(display) >= 14) {
>> >  		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>> >  	} else if (display->platform.dg2) {
>> 
>> -- 
>> Jani Nikula, Intel
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH 1/4] drm/i915/bw: Extract platform-specific parameters

[Matt Roper]

On Fri, Apr 10, 2026 at 11:39:10AM -0300, Gustavo Sousa wrote:
> Matt Roper <matthew.d.roper@intel.com> writes:
> 
> > On Wed, Apr 08, 2026 at 10:16:42PM +0300, Jani Nikula wrote:
> >> On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> >> > We got confirmation from the hardware team that the bandwidth parameters
> >> > deprogbwlimit and derating are platform-specific and not tied to the
> >> > display IP.  As such, let's make sure that we use platform checks for
> >> > those.
> >> >
> >> > The rest of the members of struct intel_sa_info are tied to the display
> >> > IP and we will deal with them as a follow-up.
> >> >
> >> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_bw.c | 174 ++++++++++++++++++++++++--------
> >> >  1 file changed, 133 insertions(+), 41 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> >> > index 474438fc1ebc..ed840b592eff 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> >> > @@ -375,77 +375,170 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
> >> >  	return dclk;
> >> >  }
> >> >  
> >> > +struct intel_platform_bw_params {
> >> > +	u8 deprogbwlimit;
> >> > +	u8 derating;
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params icl_plat_bw_params = {
> >> > +	.deprogbwlimit = 25,
> >> > +	.derating = 10,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params tgl_plat_bw_params = {
> >> > +	.deprogbwlimit = 34,
> >> > +	.derating = 10,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params rkl_plat_bw_params = {
> >> > +	.deprogbwlimit = 20,
> >> > +	.derating = 10,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params adl_s_plat_bw_params = {
> >> > +	.deprogbwlimit = 38,
> >> > +	.derating = 10,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params adl_p_plat_bw_params = {
> >> > +	.deprogbwlimit = 38,
> >> > +	.derating = 20,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params bmg_plat_bw_params = {
> >> > +	.deprogbwlimit = 53,
> >> > +	.derating = 30,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params bmg_ecc_plat_bw_params = {
> >> > +	.deprogbwlimit = 53,
> >> > +	.derating = 45,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params ptl_plat_bw_params = {
> >> > +	.deprogbwlimit = 65,
> >> > +	.derating = 10,
> >> > +};
> >> > +
> >> > +static const struct intel_platform_bw_params wcl_plat_bw_params = {
> >> > +	.deprogbwlimit = 22,
> >> > +	.derating = 10,
> >> > +};
> >> 
> >> In the above, "plat" feels like tautology, since they're all prefixed by
> >> platform acronyms.
> >
> > "soc" might be more consistent with what we (and various hardware docs)
> > do to refer to "stuff that's outside the graphics/media/display IP and
> > doesn't relate to GMD_ID version numbers."  Technically "soc" is a bit
> > of a misnomer too since a lot of our recent platforms are multi-chip and
> > not truly SoC's anymore, but the intent is still understandable.
> 
> Yeah. I intetionally prefered to use "platform" as a general term to
> refer to either SoC or multi-chip package.  Do you prefer that we name
> the struct type intel_soc_bw_params?
> 
> What about intel_display_bw_params that is added later? Is that a good
> name? I thought intel_ip_bw_params would be a bit vague, since we have
> different types of IPs (display being one of them) in the platform.

Personally I think "soc_bw_params" vs "display_bw_params" seems like a
similar distinction to what we have elsewhere in the driver (especially
if we add a 1-sentence comment above the structure clarifying what the
origin/source of those parameters is.  But I'll leave it up to Jani and
the other display experts to make the call since they're the ones who
work with this code the most.

> 
> >
> >> 
> >> > +
> >> > +static const struct intel_platform_bw_params *get_platform_bw_params(struct intel_display *display)
> >> > +{
> >> > +	const struct intel_platform_bw_params *ret;
> >> > +
> >> > +	if (display->platform.dgfx)
> >> > +		goto dgfx;
> >> > +
> >> > +	ret = &icl_plat_bw_params;
> >> > +	if (display->platform.icelake ||
> >> > +	    display->platform.jasperlake ||
> >> > +	    display->platform.elkhartlake)
> >> > +		return ret;
> >> 
> >> What's the point of assigning and returning ret?
> >> 
> >> Why not just return &icl_plat_bw_params; directly?
> >> 
> >
> > It looks like the intent might have been to let people keep copy/pasting
> > the same pattern and have the fallback at the end always default back to
> > whatever the "newest" one was if a proper match wasn't found.  But I
> > agree that the handling here feels awkward and a simple if/else ladder
> > would be preferable.
> 
> Yeah, allowing developers to easily add new platforms without too much
> churn was the intention here.  I knew this style was unconventional, but
> I thought the intent justified it (and IMO the code is still readable,
> although admittedly a bit weird).
> 
> If that's not acceptable, would something along the lines of below be
> accepted?
> 
>     if (display->platformOB.dgfx) {
>         if (...)
>              return platform_a_params;
>         else if (...)
>              return platform_b_params;
>         else if (...)
>              return platform_c_params;
>         
>         default_params = platform_c_params;
>     } else {
>         if (...)
>              return platform_d_params;
>         else if (...)
>              return platform_e_params;
>         else if (...)
>              return platform_f_params;
>         
>         default_params = platform_f_params;
>     }
>     
>     do_warning();
>     return default_params;

Yeah, I think a traditional if/else ladder like this is best.  I don't
think we even need to track a 'default_params' variable; we can just
directly return some recent platform as a fallback at the end too.  If
the fallback winds up not getting updated when we add new platforms, I
don't think that really matters since there's no real guarantee that
falling back to incorrect n-1 platform numbers is better than falling
back to incorrect n-2 platform numbers.

If we've screwed up and forgotten to add the parameters for a new
platform, then that's going to be something that's flagged almost
immediately by CI and will be quickly fixed long before the platform
ever leaves force_probe.


Matt

> --
> Gustavo Sousa
> 
> >
> >
> > Matt
> >
> >> > +
> >> > +	ret = &tgl_plat_bw_params;
> >> > +	if (display->platform.tigerlake)
> >> > +		return ret;
> >> > +
> >> > +	ret = &rkl_plat_bw_params;
> >> > +	if (display->platform.rocketlake)
> >> > +		return ret;
> >> > +
> >> > +	ret = &adl_s_plat_bw_params;
> >> > +	if (display->platform.alderlake_s)
> >> > +		return ret;
> >> > +
> >> > +	ret = &adl_p_plat_bw_params;
> >> > +	if (display->platform.alderlake_p)
> >> > +		return ret;
> >> > +
> >> > +	ret = &adl_s_plat_bw_params;
> >> > +	if (display->platform.meteorlake ||
> >> > +	    display->platform.lunarlake)
> >> > +		return ret;
> >> > +
> >> > +	ret = &ptl_plat_bw_params;
> >> > +	if (display->platform.pantherlake ||
> >> > +	    display->platform.novalake) {
> >> > +		if (display->platform.pantherlake_wildcatlake)
> >> > +			ret = &wcl_plat_bw_params;
> >> > +
> >> > +		return ret;
> >> > +	}
> >> > +
> >> > +	goto missing;
> >> > +
> >> > +dgfx:
> >> > +	ret = &tgl_plat_bw_params;
> >> > +	if (display->platform.dg1)
> >> > +		return ret;
> >> > +
> >> > +	ret = &bmg_plat_bw_params;
> >> > +	if (display->platform.battlemage) {
> >> > +		const struct dram_info *dram_info = intel_dram_info(display);
> >> > +
> >> > +		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> >> > +			ret = &bmg_ecc_plat_bw_params;
> >> > +
> >> > +		return ret;
> >> > +	}
> >> > +
> >> > +missing:
> >> > +	/*
> >> > +	 * Use parameters from the most recent platform,
> >> > +	 * but raise a warning.
> >> > +	 */
> >> > +	drm_WARN(display->drm, 1,
> >> > +		 "Platform-specific bandwidth parameters not found, using possibly incompatible default values\n");
> >> > +
> >> > +	return ret;
> >> 
> >> I don't understand at all why the function is written the way it
> >> is. Seems like it should be a regular if-ladder like we have, with zero
> >> gotos.
> >> 
> >> > +}
> >> > +
> >> >  struct intel_sa_info {
> >> >  	u16 displayrtids;
> >> > -	u8 deburst, deprogbwlimit, derating;
> >> > +	u8 deburst;
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info icl_sa_info = {
> >> >  	.deburst = 8,
> >> > -	.deprogbwlimit = 25, /* GB/s */
> >> >  	.displayrtids = 128,
> >> > -	.derating = 10,
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info tgl_sa_info = {
> >> >  	.deburst = 16,
> >> > -	.deprogbwlimit = 34, /* GB/s */
> >> >  	.displayrtids = 256,
> >> > -	.derating = 10,
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info rkl_sa_info = {
> >> >  	.deburst = 8,
> >> > -	.deprogbwlimit = 20, /* GB/s */
> >> >  	.displayrtids = 128,
> >> > -	.derating = 10,
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info adls_sa_info = {
> >> >  	.deburst = 16,
> >> > -	.deprogbwlimit = 38, /* GB/s */
> >> >  	.displayrtids = 256,
> >> > -	.derating = 10,
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info adlp_sa_info = {
> >> >  	.deburst = 16,
> >> > -	.deprogbwlimit = 38, /* GB/s */
> >> >  	.displayrtids = 256,
> >> > -	.derating = 20,
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info mtl_sa_info = {
> >> >  	.deburst = 32,
> >> > -	.deprogbwlimit = 38, /* GB/s */
> >> >  	.displayrtids = 256,
> >> > -	.derating = 10,
> >> > -};
> >> > -
> >> > -static const struct intel_sa_info xe2_hpd_sa_info = {
> >> > -	.derating = 30,
> >> > -	.deprogbwlimit = 53,
> >> > -	/* Other values not used by simplified algorithm */
> >> > -};
> >> > -
> >> > -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
> >> > -	.derating = 45,
> >> > -	.deprogbwlimit = 53,
> >> > -	/* Other values not used by simplified algorithm */
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info xe3lpd_sa_info = {
> >> >  	.deburst = 32,
> >> > -	.deprogbwlimit = 65, /* GB/s */
> >> >  	.displayrtids = 256,
> >> > -	.derating = 10,
> >> >  };
> >> >  
> >> >  static const struct intel_sa_info xe3lpd_3002_sa_info = {
> >> >  	.deburst = 32,
> >> > -	.deprogbwlimit = 22, /* GB/s */
> >> >  	.displayrtids = 256,
> >> > -	.derating = 10,
> >> >  };
> >> >  
> >> >  static int icl_get_bw_info(struct intel_display *display,
> >> > @@ -453,6 +546,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >> >  			   const struct intel_sa_info *sa)
> >> >  {
> >> >  	struct intel_qgv_info qi = {};
> >> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> >> 
> >> Perhaps it would be better to pass this in instead of every function
> >> having the call.
> >> 
> >> Nitpick, "plat" is not an abbreviation I'm fond of.
> >> 
> >> >  	bool is_y_tile = true; /* assume y tile may be used */
> >> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
> >> >  	int ipqdepth, ipqdepthpch = 16;
> >> > @@ -469,7 +563,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >> >  	}
> >> >  
> >> >  	dclk_max = icl_sagv_max_dclk(&qi);
> >> > -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> >> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> >> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> >> >  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
> >> >  
> >> > @@ -499,7 +593,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
> >> >  
> >> >  			bi->deratedbw[j] = min(maxdebw,
> >> > -					       bw * (100 - sa->derating) / 100);
> >> > +					       bw * (100 - plat_bw_params->derating) / 100);
> >> >  
> >> >  			drm_dbg_kms(display->drm,
> >> >  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> >> > @@ -524,6 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >> >  			   const struct intel_sa_info *sa)
> >> >  {
> >> >  	struct intel_qgv_info qi = {};
> >> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> >> >  	bool is_y_tile = true; /* assume y tile may be used */
> >> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
> >> >  	int ipqdepth, ipqdepthpch = 16;
> >> > @@ -557,7 +652,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >> >  	dclk_max = icl_sagv_max_dclk(&qi);
> >> >  
> >> >  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
> >> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> >> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> >> >  
> >> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> >> >  	/*
> >> > @@ -602,7 +697,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
> >> >  
> >> >  			bi->deratedbw[j] = min(maxdebw,
> >> > -					       bw * (100 - sa->derating) / 100);
> >> > +					       bw * (100 - plat_bw_params->derating) / 100);
> >> >  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
> >> >  							  num_channels *
> >> >  							  qi.channel_width, 8);
> >> > @@ -663,10 +758,10 @@ static void dg2_get_bw_info(struct intel_display *display)
> >> >  }
> >> >  
> >> >  static int xe2_hpd_get_bw_info(struct intel_display *display,
> >> > -			       const struct dram_info *dram_info,
> >> > -			       const struct intel_sa_info *sa)
> >> > +			       const struct dram_info *dram_info)
> >> >  {
> >> >  	struct intel_qgv_info qi = {};
> >> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> >> >  	int num_channels = dram_info->num_channels;
> >> >  	int peakbw, maxdebw;
> >> >  	int ret, i;
> >> > @@ -679,14 +774,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
> >> >  	}
> >> >  
> >> >  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
> >> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
> >> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
> >> >  
> >> >  	for (i = 0; i < qi.num_points; i++) {
> >> >  		const struct intel_qgv_point *point = &qi.points[i];
> >> >  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
> >> >  
> >> >  		display->bw.max[0].deratedbw[i] =
> >> > -			min(maxdebw, (100 - sa->derating) * bw / 100);
> >> > +			min(maxdebw, (100 - plat_bw_params->derating) * bw / 100);
> >> >  		display->bw.max[0].peakbw[i] = bw;
> >> >  
> >> >  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
> >> > @@ -814,10 +909,7 @@ void intel_bw_init_hw(struct intel_display *display)
> >> >  		else
> >> >  			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> >> >  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> >> > -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> >> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
> >> > -		else
> >> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
> >> > +		xe2_hpd_get_bw_info(display, dram_info);
> >> >  	} else if (DISPLAY_VER(display) >= 14) {
> >> >  		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
> >> >  	} else if (display->platform.dg2) {
> >> 
> >> -- 
> >> Jani Nikula, Intel
> >
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 1/4] drm/i915/bw: Extract platform-specific parameters

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Fri, Apr 10, 2026 at 11:39:10AM -0300, Gustavo Sousa wrote:
>> Matt Roper <matthew.d.roper@intel.com> writes:
>> 
>> > On Wed, Apr 08, 2026 at 10:16:42PM +0300, Jani Nikula wrote:
>> >> On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> >> > We got confirmation from the hardware team that the bandwidth parameters
>> >> > deprogbwlimit and derating are platform-specific and not tied to the
>> >> > display IP.  As such, let's make sure that we use platform checks for
>> >> > those.
>> >> >
>> >> > The rest of the members of struct intel_sa_info are tied to the display
>> >> > IP and we will deal with them as a follow-up.
>> >> >
>> >> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> >> > ---
>> >> >  drivers/gpu/drm/i915/display/intel_bw.c | 174 ++++++++++++++++++++++++--------
>> >> >  1 file changed, 133 insertions(+), 41 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> >> > index 474438fc1ebc..ed840b592eff 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> >> > @@ -375,77 +375,170 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>> >> >  	return dclk;
>> >> >  }
>> >> >  
>> >> > +struct intel_platform_bw_params {
>> >> > +	u8 deprogbwlimit;
>> >> > +	u8 derating;
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params icl_plat_bw_params = {
>> >> > +	.deprogbwlimit = 25,
>> >> > +	.derating = 10,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params tgl_plat_bw_params = {
>> >> > +	.deprogbwlimit = 34,
>> >> > +	.derating = 10,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params rkl_plat_bw_params = {
>> >> > +	.deprogbwlimit = 20,
>> >> > +	.derating = 10,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params adl_s_plat_bw_params = {
>> >> > +	.deprogbwlimit = 38,
>> >> > +	.derating = 10,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params adl_p_plat_bw_params = {
>> >> > +	.deprogbwlimit = 38,
>> >> > +	.derating = 20,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params bmg_plat_bw_params = {
>> >> > +	.deprogbwlimit = 53,
>> >> > +	.derating = 30,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params bmg_ecc_plat_bw_params = {
>> >> > +	.deprogbwlimit = 53,
>> >> > +	.derating = 45,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params ptl_plat_bw_params = {
>> >> > +	.deprogbwlimit = 65,
>> >> > +	.derating = 10,
>> >> > +};
>> >> > +
>> >> > +static const struct intel_platform_bw_params wcl_plat_bw_params = {
>> >> > +	.deprogbwlimit = 22,
>> >> > +	.derating = 10,
>> >> > +};
>> >> 
>> >> In the above, "plat" feels like tautology, since they're all prefixed by
>> >> platform acronyms.
>> >
>> > "soc" might be more consistent with what we (and various hardware docs)
>> > do to refer to "stuff that's outside the graphics/media/display IP and
>> > doesn't relate to GMD_ID version numbers."  Technically "soc" is a bit
>> > of a misnomer too since a lot of our recent platforms are multi-chip and
>> > not truly SoC's anymore, but the intent is still understandable.
>> 
>> Yeah. I intetionally prefered to use "platform" as a general term to
>> refer to either SoC or multi-chip package.  Do you prefer that we name
>> the struct type intel_soc_bw_params?
>> 
>> What about intel_display_bw_params that is added later? Is that a good
>> name? I thought intel_ip_bw_params would be a bit vague, since we have
>> different types of IPs (display being one of them) in the platform.
>
> Personally I think "soc_bw_params" vs "display_bw_params" seems like a
> similar distinction to what we have elsewhere in the driver (especially
> if we add a 1-sentence comment above the structure clarifying what the
> origin/source of those parameters is.  But I'll leave it up to Jani and
> the other display experts to make the call since they're the ones who
> work with this code the most.
>
>> 
>> >
>> >> 
>> >> > +
>> >> > +static const struct intel_platform_bw_params *get_platform_bw_params(struct intel_display *display)
>> >> > +{
>> >> > +	const struct intel_platform_bw_params *ret;
>> >> > +
>> >> > +	if (display->platform.dgfx)
>> >> > +		goto dgfx;
>> >> > +
>> >> > +	ret = &icl_plat_bw_params;
>> >> > +	if (display->platform.icelake ||
>> >> > +	    display->platform.jasperlake ||
>> >> > +	    display->platform.elkhartlake)
>> >> > +		return ret;
>> >> 
>> >> What's the point of assigning and returning ret?
>> >> 
>> >> Why not just return &icl_plat_bw_params; directly?
>> >> 
>> >
>> > It looks like the intent might have been to let people keep copy/pasting
>> > the same pattern and have the fallback at the end always default back to
>> > whatever the "newest" one was if a proper match wasn't found.  But I
>> > agree that the handling here feels awkward and a simple if/else ladder
>> > would be preferable.
>> 
>> Yeah, allowing developers to easily add new platforms without too much
>> churn was the intention here.  I knew this style was unconventional, but
>> I thought the intent justified it (and IMO the code is still readable,
>> although admittedly a bit weird).
>> 
>> If that's not acceptable, would something along the lines of below be
>> accepted?
>> 
>>     if (display->platformOB.dgfx) {
>>         if (...)
>>              return platform_a_params;
>>         else if (...)
>>              return platform_b_params;
>>         else if (...)
>>              return platform_c_params;
>>         
>>         default_params = platform_c_params;
>>     } else {
>>         if (...)
>>              return platform_d_params;
>>         else if (...)
>>              return platform_e_params;
>>         else if (...)
>>              return platform_f_params;
>>         
>>         default_params = platform_f_params;
>>     }
>>     
>>     do_warning();
>>     return default_params;
>
> Yeah, I think a traditional if/else ladder like this is best.  I don't
> think we even need to track a 'default_params' variable; we can just
> directly return some recent platform as a fallback at the end too.  If
> the fallback winds up not getting updated when we add new platforms, I
> don't think that really matters since there's no real guarantee that
> falling back to incorrect n-1 platform numbers is better than falling
> back to incorrect n-2 platform numbers.

Well, I would like to make a distinction between client and discrete
(e.g. there is a significant difference between BMG's and
PTL's derating param).  That would be the reason for the default_params
variable, which would allow a single place to raise the warning.

>
> If we've screwed up and forgotten to add the parameters for a new
> platform, then that's going to be something that's flagged almost
> immediately by CI and will be quickly fixed long before the platform
> ever leaves force_probe.

Yeah, true.  Another possibility is to just return NULL and purposefully
cause anull-pointer dereference; or even have the default being all
zeros, so that we don't worry about updating the default from time to
time.

--
Gustavo Sousa

>
>
> Matt
>
>> --
>> Gustavo Sousa
>> 
>> >
>> >
>> > Matt
>> >
>> >> > +
>> >> > +	ret = &tgl_plat_bw_params;
>> >> > +	if (display->platform.tigerlake)
>> >> > +		return ret;
>> >> > +
>> >> > +	ret = &rkl_plat_bw_params;
>> >> > +	if (display->platform.rocketlake)
>> >> > +		return ret;
>> >> > +
>> >> > +	ret = &adl_s_plat_bw_params;
>> >> > +	if (display->platform.alderlake_s)
>> >> > +		return ret;
>> >> > +
>> >> > +	ret = &adl_p_plat_bw_params;
>> >> > +	if (display->platform.alderlake_p)
>> >> > +		return ret;
>> >> > +
>> >> > +	ret = &adl_s_plat_bw_params;
>> >> > +	if (display->platform.meteorlake ||
>> >> > +	    display->platform.lunarlake)
>> >> > +		return ret;
>> >> > +
>> >> > +	ret = &ptl_plat_bw_params;
>> >> > +	if (display->platform.pantherlake ||
>> >> > +	    display->platform.novalake) {
>> >> > +		if (display->platform.pantherlake_wildcatlake)
>> >> > +			ret = &wcl_plat_bw_params;
>> >> > +
>> >> > +		return ret;
>> >> > +	}
>> >> > +
>> >> > +	goto missing;
>> >> > +
>> >> > +dgfx:
>> >> > +	ret = &tgl_plat_bw_params;
>> >> > +	if (display->platform.dg1)
>> >> > +		return ret;
>> >> > +
>> >> > +	ret = &bmg_plat_bw_params;
>> >> > +	if (display->platform.battlemage) {
>> >> > +		const struct dram_info *dram_info = intel_dram_info(display);
>> >> > +
>> >> > +		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> >> > +			ret = &bmg_ecc_plat_bw_params;
>> >> > +
>> >> > +		return ret;
>> >> > +	}
>> >> > +
>> >> > +missing:
>> >> > +	/*
>> >> > +	 * Use parameters from the most recent platform,
>> >> > +	 * but raise a warning.
>> >> > +	 */
>> >> > +	drm_WARN(display->drm, 1,
>> >> > +		 "Platform-specific bandwidth parameters not found, using possibly incompatible default values\n");
>> >> > +
>> >> > +	return ret;
>> >> 
>> >> I don't understand at all why the function is written the way it
>> >> is. Seems like it should be a regular if-ladder like we have, with zero
>> >> gotos.
>> >> 
>> >> > +}
>> >> > +
>> >> >  struct intel_sa_info {
>> >> >  	u16 displayrtids;
>> >> > -	u8 deburst, deprogbwlimit, derating;
>> >> > +	u8 deburst;
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info icl_sa_info = {
>> >> >  	.deburst = 8,
>> >> > -	.deprogbwlimit = 25, /* GB/s */
>> >> >  	.displayrtids = 128,
>> >> > -	.derating = 10,
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info tgl_sa_info = {
>> >> >  	.deburst = 16,
>> >> > -	.deprogbwlimit = 34, /* GB/s */
>> >> >  	.displayrtids = 256,
>> >> > -	.derating = 10,
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info rkl_sa_info = {
>> >> >  	.deburst = 8,
>> >> > -	.deprogbwlimit = 20, /* GB/s */
>> >> >  	.displayrtids = 128,
>> >> > -	.derating = 10,
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info adls_sa_info = {
>> >> >  	.deburst = 16,
>> >> > -	.deprogbwlimit = 38, /* GB/s */
>> >> >  	.displayrtids = 256,
>> >> > -	.derating = 10,
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info adlp_sa_info = {
>> >> >  	.deburst = 16,
>> >> > -	.deprogbwlimit = 38, /* GB/s */
>> >> >  	.displayrtids = 256,
>> >> > -	.derating = 20,
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info mtl_sa_info = {
>> >> >  	.deburst = 32,
>> >> > -	.deprogbwlimit = 38, /* GB/s */
>> >> >  	.displayrtids = 256,
>> >> > -	.derating = 10,
>> >> > -};
>> >> > -
>> >> > -static const struct intel_sa_info xe2_hpd_sa_info = {
>> >> > -	.derating = 30,
>> >> > -	.deprogbwlimit = 53,
>> >> > -	/* Other values not used by simplified algorithm */
>> >> > -};
>> >> > -
>> >> > -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>> >> > -	.derating = 45,
>> >> > -	.deprogbwlimit = 53,
>> >> > -	/* Other values not used by simplified algorithm */
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info xe3lpd_sa_info = {
>> >> >  	.deburst = 32,
>> >> > -	.deprogbwlimit = 65, /* GB/s */
>> >> >  	.displayrtids = 256,
>> >> > -	.derating = 10,
>> >> >  };
>> >> >  
>> >> >  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>> >> >  	.deburst = 32,
>> >> > -	.deprogbwlimit = 22, /* GB/s */
>> >> >  	.displayrtids = 256,
>> >> > -	.derating = 10,
>> >> >  };
>> >> >  
>> >> >  static int icl_get_bw_info(struct intel_display *display,
>> >> > @@ -453,6 +546,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> >> >  			   const struct intel_sa_info *sa)
>> >> >  {
>> >> >  	struct intel_qgv_info qi = {};
>> >> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> >> 
>> >> Perhaps it would be better to pass this in instead of every function
>> >> having the call.
>> >> 
>> >> Nitpick, "plat" is not an abbreviation I'm fond of.
>> >> 
>> >> >  	bool is_y_tile = true; /* assume y tile may be used */
>> >> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>> >> >  	int ipqdepth, ipqdepthpch = 16;
>> >> > @@ -469,7 +563,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> >> >  	}
>> >> >  
>> >> >  	dclk_max = icl_sagv_max_dclk(&qi);
>> >> > -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> >> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> >> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> >> >  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>> >> >  
>> >> > @@ -499,7 +593,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> >> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>> >> >  
>> >> >  			bi->deratedbw[j] = min(maxdebw,
>> >> > -					       bw * (100 - sa->derating) / 100);
>> >> > +					       bw * (100 - plat_bw_params->derating) / 100);
>> >> >  
>> >> >  			drm_dbg_kms(display->drm,
>> >> >  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>> >> > @@ -524,6 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> >> >  			   const struct intel_sa_info *sa)
>> >> >  {
>> >> >  	struct intel_qgv_info qi = {};
>> >> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> >> >  	bool is_y_tile = true; /* assume y tile may be used */
>> >> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>> >> >  	int ipqdepth, ipqdepthpch = 16;
>> >> > @@ -557,7 +652,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> >> >  	dclk_max = icl_sagv_max_dclk(&qi);
>> >> >  
>> >> >  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>> >> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> >> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> >> >  
>> >> >  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> >> >  	/*
>> >> > @@ -602,7 +697,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> >> >  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>> >> >  
>> >> >  			bi->deratedbw[j] = min(maxdebw,
>> >> > -					       bw * (100 - sa->derating) / 100);
>> >> > +					       bw * (100 - plat_bw_params->derating) / 100);
>> >> >  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>> >> >  							  num_channels *
>> >> >  							  qi.channel_width, 8);
>> >> > @@ -663,10 +758,10 @@ static void dg2_get_bw_info(struct intel_display *display)
>> >> >  }
>> >> >  
>> >> >  static int xe2_hpd_get_bw_info(struct intel_display *display,
>> >> > -			       const struct dram_info *dram_info,
>> >> > -			       const struct intel_sa_info *sa)
>> >> > +			       const struct dram_info *dram_info)
>> >> >  {
>> >> >  	struct intel_qgv_info qi = {};
>> >> > +	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> >> >  	int num_channels = dram_info->num_channels;
>> >> >  	int peakbw, maxdebw;
>> >> >  	int ret, i;
>> >> > @@ -679,14 +774,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>> >> >  	}
>> >> >  
>> >> >  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>> >> > -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> >> > +	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> >> >  
>> >> >  	for (i = 0; i < qi.num_points; i++) {
>> >> >  		const struct intel_qgv_point *point = &qi.points[i];
>> >> >  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>> >> >  
>> >> >  		display->bw.max[0].deratedbw[i] =
>> >> > -			min(maxdebw, (100 - sa->derating) * bw / 100);
>> >> > +			min(maxdebw, (100 - plat_bw_params->derating) * bw / 100);
>> >> >  		display->bw.max[0].peakbw[i] = bw;
>> >> >  
>> >> >  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>> >> > @@ -814,10 +909,7 @@ void intel_bw_init_hw(struct intel_display *display)
>> >> >  		else
>> >> >  			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> >> >  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>> >> > -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> >> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>> >> > -		else
>> >> > -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>> >> > +		xe2_hpd_get_bw_info(display, dram_info);
>> >> >  	} else if (DISPLAY_VER(display) >= 14) {
>> >> >  		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>> >> >  	} else if (display->platform.dg2) {
>> >> 
>> >> -- 
>> >> Jani Nikula, Intel
>> >
>> > -- 
>> > Matt Roper
>> > Graphics Software Engineer
>> > Linux GPU Platform Enablement
>> > Intel Corporation
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

[PATCH 2/4] drm/i915/bw: Deduplicate intel_sa_info instances

[Gustavo Sousa]

Now that intel_sa_info contains bandwidth parameters specific to the
display IP, we can drop many duplicates and reuse from previous
releases.

Let's do that and also simplify intel_bw_init_hw() while at it.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 44 ++++++---------------------------
 1 file changed, 8 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ed840b592eff..654876215ace 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -516,27 +516,7 @@ static const struct intel_sa_info rkl_sa_info = {
 	.displayrtids = 128,
 };
 
-static const struct intel_sa_info adls_sa_info = {
-	.deburst = 16,
-	.displayrtids = 256,
-};
-
-static const struct intel_sa_info adlp_sa_info = {
-	.deburst = 16,
-	.displayrtids = 256,
-};
-
-static const struct intel_sa_info mtl_sa_info = {
-	.deburst = 32,
-	.displayrtids = 256,
-};
-
-static const struct intel_sa_info xe3lpd_sa_info = {
-	.deburst = 32,
-	.displayrtids = 256,
-};
-
-static const struct intel_sa_info xe3lpd_3002_sa_info = {
+static const struct intel_sa_info xelpdp_sa_info = {
 	.deburst = 32,
 	.displayrtids = 256,
 };
@@ -903,25 +883,17 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (DISPLAY_VER(display) >= 35)
 		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
 
-	if (DISPLAY_VER(display) >= 30) {
-		if (DISPLAY_VERx100(display) == 3002)
-			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
-		else
-			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
-	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
 		xe2_hpd_get_bw_info(display, dram_info);
 	} else if (DISPLAY_VER(display) >= 14) {
-		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
+		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
 	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
-	} else if (display->platform.alderlake_p) {
-		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
-	} else if (display->platform.alderlake_s) {
-		tgl_get_bw_info(display, dram_info, &adls_sa_info);
-	} else if (display->platform.rocketlake) {
-		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
-	} else if (DISPLAY_VER(display) == 12) {
-		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
+	} else if (DISPLAY_VER(display) >= 12) {
+		if (display->platform.rocketlake)
+			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
+		else
+			tgl_get_bw_info(display, dram_info, &tgl_sa_info);
 	} else if (DISPLAY_VER(display) == 11) {
 		icl_get_bw_info(display, dram_info, &icl_sa_info);
 	}

-- 
2.53.0

Re: [PATCH 2/4] drm/i915/bw: Deduplicate intel_sa_info instances

[Matt Roper]

On Wed, Apr 08, 2026 at 03:53:00PM -0300, Gustavo Sousa wrote:
> Now that intel_sa_info contains bandwidth parameters specific to the
> display IP, we can drop many duplicates and reuse from previous
> releases.
> 
> Let's do that and also simplify intel_bw_init_hw() while at it.
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 44 ++++++---------------------------
>  1 file changed, 8 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index ed840b592eff..654876215ace 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -516,27 +516,7 @@ static const struct intel_sa_info rkl_sa_info = {
>  	.displayrtids = 128,
>  };
>  
> -static const struct intel_sa_info adls_sa_info = {
> -	.deburst = 16,
> -	.displayrtids = 256,
> -};
> -
> -static const struct intel_sa_info adlp_sa_info = {
> -	.deburst = 16,
> -	.displayrtids = 256,
> -};
> -
> -static const struct intel_sa_info mtl_sa_info = {
> -	.deburst = 32,
> -	.displayrtids = 256,
> -};
> -
> -static const struct intel_sa_info xe3lpd_sa_info = {
> -	.deburst = 32,
> -	.displayrtids = 256,
> -};
> -
> -static const struct intel_sa_info xe3lpd_3002_sa_info = {
> +static const struct intel_sa_info xelpdp_sa_info = {
>  	.deburst = 32,
>  	.displayrtids = 256,
>  };
> @@ -903,25 +883,17 @@ void intel_bw_init_hw(struct intel_display *display)
>  	if (DISPLAY_VER(display) >= 35)
>  		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
>  
> -	if (DISPLAY_VER(display) >= 30) {
> -		if (DISPLAY_VERx100(display) == 3002)
> -			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
> -		else
> -			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> -	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> +	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>  		xe2_hpd_get_bw_info(display, dram_info);
>  	} else if (DISPLAY_VER(display) >= 14) {
> -		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
> +		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
>  	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
> -	} else if (display->platform.alderlake_p) {
> -		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
> -	} else if (display->platform.alderlake_s) {
> -		tgl_get_bw_info(display, dram_info, &adls_sa_info);
> -	} else if (display->platform.rocketlake) {
> -		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> -	} else if (DISPLAY_VER(display) == 12) {
> -		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> +	} else if (DISPLAY_VER(display) >= 12) {
> +		if (display->platform.rocketlake)
> +			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> +		else
> +			tgl_get_bw_info(display, dram_info, &tgl_sa_info);

It seems strange to need to need to drop back to a platform check here
on something that's supposed to be tied to IP version.  But if I recall
correctly, RKL was a bit of a strange frankenstein platform where TGL's
"gen12" IP got backported onto an ICL-style chassis, which caused it to
inherit various ICL traits despite the new IP.  It might actually be
more clear to just re-use the icl_sa_info for that one and leave a
comment admitting that yeah, RKL was an oddball platform that didn't
really follow the rules.

We might also want to rename tgl_sa_info to "gen12_sa_info" since that's
a more accurate description (and is the last version where we're allowed
to use the "gen" terminology rather than the new marketing names for the
IP).  By similar logic, "icl_sa_info" should become "gen11_sa_info"
since it does indeed get used on the other gen11 platforms too
(jsl/ehl).


Matt

>  	} else if (DISPLAY_VER(display) == 11) {
>  		icl_get_bw_info(display, dram_info, &icl_sa_info);
>  	}
> 
> -- 
> 2.53.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 2/4] drm/i915/bw: Deduplicate intel_sa_info instances

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Wed, Apr 08, 2026 at 03:53:00PM -0300, Gustavo Sousa wrote:
>> Now that intel_sa_info contains bandwidth parameters specific to the
>> display IP, we can drop many duplicates and reuse from previous
>> releases.
>> 
>> Let's do that and also simplify intel_bw_init_hw() while at it.
>> 
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 44 ++++++---------------------------
>>  1 file changed, 8 insertions(+), 36 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index ed840b592eff..654876215ace 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -516,27 +516,7 @@ static const struct intel_sa_info rkl_sa_info = {
>>  	.displayrtids = 128,
>>  };
>>  
>> -static const struct intel_sa_info adls_sa_info = {
>> -	.deburst = 16,
>> -	.displayrtids = 256,
>> -};
>> -
>> -static const struct intel_sa_info adlp_sa_info = {
>> -	.deburst = 16,
>> -	.displayrtids = 256,
>> -};
>> -
>> -static const struct intel_sa_info mtl_sa_info = {
>> -	.deburst = 32,
>> -	.displayrtids = 256,
>> -};
>> -
>> -static const struct intel_sa_info xe3lpd_sa_info = {
>> -	.deburst = 32,
>> -	.displayrtids = 256,
>> -};
>> -
>> -static const struct intel_sa_info xe3lpd_3002_sa_info = {
>> +static const struct intel_sa_info xelpdp_sa_info = {
>>  	.deburst = 32,
>>  	.displayrtids = 256,
>>  };
>> @@ -903,25 +883,17 @@ void intel_bw_init_hw(struct intel_display *display)
>>  	if (DISPLAY_VER(display) >= 35)
>>  		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
>>  
>> -	if (DISPLAY_VER(display) >= 30) {
>> -		if (DISPLAY_VERx100(display) == 3002)
>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>> -		else
>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> -	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>> +	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>>  		xe2_hpd_get_bw_info(display, dram_info);
>>  	} else if (DISPLAY_VER(display) >= 14) {
>> -		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>> +		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
>>  	} else if (display->platform.dg2) {
>>  		dg2_get_bw_info(display);
>> -	} else if (display->platform.alderlake_p) {
>> -		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
>> -	} else if (display->platform.alderlake_s) {
>> -		tgl_get_bw_info(display, dram_info, &adls_sa_info);
>> -	} else if (display->platform.rocketlake) {
>> -		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>> -	} else if (DISPLAY_VER(display) == 12) {
>> -		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>> +	} else if (DISPLAY_VER(display) >= 12) {
>> +		if (display->platform.rocketlake)
>> +			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>> +		else
>> +			tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>
> It seems strange to need to need to drop back to a platform check here
> on something that's supposed to be tied to IP version.  But if I recall
> correctly, RKL was a bit of a strange frankenstein platform where TGL's
> "gen12" IP got backported onto an ICL-style chassis, which caused it to
> inherit various ICL traits despite the new IP.  It might actually be
> more clear to just re-use the icl_sa_info for that one and leave a
> comment admitting that yeah, RKL was an oddball platform that didn't
> really follow the rules.

Huh.  Yep, using icl_sa_info sounds good; I totally missed the fact that
rkl_sa_info matched icl_sa_info.

>
> We might also want to rename tgl_sa_info to "gen12_sa_info" since that's
> a more accurate description (and is the last version where we're allowed
> to use the "gen" terminology rather than the new marketing names for the
> IP).  By similar logic, "icl_sa_info" should become "gen11_sa_info"
> since it does indeed get used on the other gen11 platforms too
> (jsl/ehl).

Sounds good.  Since I'm renaming the struct type name to
intel_display_bw_params (to indicate that those are tied to the display
IP) in a separate patch, I think it makes sense to do the instances
renaming there as well.  Ack on moving back to mtl_sa_info here and then
doing all renaming in the patch that also renames the struct type?

--
Gustavo Sousa

>
>
> Matt
>
>>  	} else if (DISPLAY_VER(display) == 11) {
>>  		icl_get_bw_info(display, dram_info, &icl_sa_info);
>>  	}
>> 
>> -- 
>> 2.53.0
>> 
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH 2/4] drm/i915/bw: Deduplicate intel_sa_info instances

[Matt Roper]

On Fri, Apr 10, 2026 at 11:49:14AM -0300, Gustavo Sousa wrote:
> Matt Roper <matthew.d.roper@intel.com> writes:
> 
> > On Wed, Apr 08, 2026 at 03:53:00PM -0300, Gustavo Sousa wrote:
> >> Now that intel_sa_info contains bandwidth parameters specific to the
> >> display IP, we can drop many duplicates and reuse from previous
> >> releases.
> >> 
> >> Let's do that and also simplify intel_bw_init_hw() while at it.
> >> 
> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_bw.c | 44 ++++++---------------------------
> >>  1 file changed, 8 insertions(+), 36 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> >> index ed840b592eff..654876215ace 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> >> @@ -516,27 +516,7 @@ static const struct intel_sa_info rkl_sa_info = {
> >>  	.displayrtids = 128,
> >>  };
> >>  
> >> -static const struct intel_sa_info adls_sa_info = {
> >> -	.deburst = 16,
> >> -	.displayrtids = 256,
> >> -};
> >> -
> >> -static const struct intel_sa_info adlp_sa_info = {
> >> -	.deburst = 16,
> >> -	.displayrtids = 256,
> >> -};
> >> -
> >> -static const struct intel_sa_info mtl_sa_info = {
> >> -	.deburst = 32,
> >> -	.displayrtids = 256,
> >> -};
> >> -
> >> -static const struct intel_sa_info xe3lpd_sa_info = {
> >> -	.deburst = 32,
> >> -	.displayrtids = 256,
> >> -};
> >> -
> >> -static const struct intel_sa_info xe3lpd_3002_sa_info = {
> >> +static const struct intel_sa_info xelpdp_sa_info = {
> >>  	.deburst = 32,
> >>  	.displayrtids = 256,
> >>  };
> >> @@ -903,25 +883,17 @@ void intel_bw_init_hw(struct intel_display *display)
> >>  	if (DISPLAY_VER(display) >= 35)
> >>  		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
> >>  
> >> -	if (DISPLAY_VER(display) >= 30) {
> >> -		if (DISPLAY_VERx100(display) == 3002)
> >> -			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
> >> -		else
> >> -			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> >> -	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> >> +	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> >>  		xe2_hpd_get_bw_info(display, dram_info);
> >>  	} else if (DISPLAY_VER(display) >= 14) {
> >> -		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
> >> +		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
> >>  	} else if (display->platform.dg2) {
> >>  		dg2_get_bw_info(display);
> >> -	} else if (display->platform.alderlake_p) {
> >> -		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
> >> -	} else if (display->platform.alderlake_s) {
> >> -		tgl_get_bw_info(display, dram_info, &adls_sa_info);
> >> -	} else if (display->platform.rocketlake) {
> >> -		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> >> -	} else if (DISPLAY_VER(display) == 12) {
> >> -		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> >> +	} else if (DISPLAY_VER(display) >= 12) {
> >> +		if (display->platform.rocketlake)
> >> +			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> >> +		else
> >> +			tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> >
> > It seems strange to need to need to drop back to a platform check here
> > on something that's supposed to be tied to IP version.  But if I recall
> > correctly, RKL was a bit of a strange frankenstein platform where TGL's
> > "gen12" IP got backported onto an ICL-style chassis, which caused it to
> > inherit various ICL traits despite the new IP.  It might actually be
> > more clear to just re-use the icl_sa_info for that one and leave a
> > comment admitting that yeah, RKL was an oddball platform that didn't
> > really follow the rules.
> 
> Huh.  Yep, using icl_sa_info sounds good; I totally missed the fact that
> rkl_sa_info matched icl_sa_info.
> 
> >
> > We might also want to rename tgl_sa_info to "gen12_sa_info" since that's
> > a more accurate description (and is the last version where we're allowed
> > to use the "gen" terminology rather than the new marketing names for the
> > IP).  By similar logic, "icl_sa_info" should become "gen11_sa_info"
> > since it does indeed get used on the other gen11 platforms too
> > (jsl/ehl).
> 
> Sounds good.  Since I'm renaming the struct type name to
> intel_display_bw_params (to indicate that those are tied to the display
> IP) in a separate patch, I think it makes sense to do the instances
> renaming there as well.  Ack on moving back to mtl_sa_info here and then
> doing all renaming in the patch that also renames the struct type?

Yeah, doing all the renames in a dedicated patch sounds fine to me.


Matt

> 
> --
> Gustavo Sousa
> 
> >
> >
> > Matt
> >
> >>  	} else if (DISPLAY_VER(display) == 11) {
> >>  		icl_get_bw_info(display, dram_info, &icl_sa_info);
> >>  	}
> >> 
> >> -- 
> >> 2.53.0
> >> 
> >
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH 3/4] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params

[Gustavo Sousa]

To align with struct intel_platform_bw_params, rename struct
intel_sa_info to intel_display_bw_params.  Also add comments to contrast
their purposes.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 38 ++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 654876215ace..64c6f18346bb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -375,6 +375,10 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
 	return dclk;
 }
 
+/*
+ * Bandwidth parameters that are tied to the platform (as opposed to struct
+ * intel_display_bw_params).
+ */
 struct intel_platform_bw_params {
 	u8 deprogbwlimit;
 	u8 derating;
@@ -496,34 +500,38 @@ static const struct intel_platform_bw_params *get_platform_bw_params(struct inte
 	return ret;
 }
 
-struct intel_sa_info {
+/*
+ * Bandwidth parameters that are tied to the display IP (as opposed to struct
+ * intel_platform_bw_params).
+ */
+struct intel_display_bw_params {
 	u16 displayrtids;
 	u8 deburst;
 };
 
-static const struct intel_sa_info icl_sa_info = {
+static const struct intel_display_bw_params icl_disp_bw_params = {
 	.deburst = 8,
 	.displayrtids = 128,
 };
 
-static const struct intel_sa_info tgl_sa_info = {
+static const struct intel_display_bw_params tgl_disp_bw_params = {
 	.deburst = 16,
 	.displayrtids = 256,
 };
 
-static const struct intel_sa_info rkl_sa_info = {
+static const struct intel_display_bw_params rkl_disp_bw_params = {
 	.deburst = 8,
 	.displayrtids = 128,
 };
 
-static const struct intel_sa_info xelpdp_sa_info = {
+static const struct intel_display_bw_params xelpdp_disp_bw_params = {
 	.deburst = 32,
 	.displayrtids = 256,
 };
 
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
-			   const struct intel_sa_info *sa)
+			   const struct intel_display_bw_params *disp_bw_params)
 {
 	struct intel_qgv_info qi = {};
 	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
@@ -544,7 +552,7 @@ static int icl_get_bw_info(struct intel_display *display,
 
 	dclk_max = icl_sagv_max_dclk(&qi);
 	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
-	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
+	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
 	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
 
 	for (i = 0; i < num_groups; i++) {
@@ -552,7 +560,7 @@ static int icl_get_bw_info(struct intel_display *display,
 		int clpchgroup;
 		int j;
 
-		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
+		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
 		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
 
 		bi->num_qgv_points = qi.num_points;
@@ -595,7 +603,7 @@ static int icl_get_bw_info(struct intel_display *display,
 
 static int tgl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
-			   const struct intel_sa_info *sa)
+			   const struct intel_display_bw_params *disp_bw_params)
 {
 	struct intel_qgv_info qi = {};
 	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
@@ -634,7 +642,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
 	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
 
-	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
+	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
 	/*
 	 * clperchgroup = 4kpagespermempage * clperchperblock,
 	 * clperchperblock = 8 / num_channels * interleave
@@ -647,7 +655,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 		int clpchgroup;
 		int j;
 
-		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
+		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
 
 		if (i < num_groups - 1) {
 			bi_next = &display->bw.max[i + 1];
@@ -886,16 +894,16 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
 		xe2_hpd_get_bw_info(display, dram_info);
 	} else if (DISPLAY_VER(display) >= 14) {
-		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
+		tgl_get_bw_info(display, dram_info, &xelpdp_disp_bw_params);
 	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
 	} else if (DISPLAY_VER(display) >= 12) {
 		if (display->platform.rocketlake)
-			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
+			tgl_get_bw_info(display, dram_info, &rkl_disp_bw_params);
 		else
-			tgl_get_bw_info(display, dram_info, &tgl_sa_info);
+			tgl_get_bw_info(display, dram_info, &tgl_disp_bw_params);
 	} else if (DISPLAY_VER(display) == 11) {
-		icl_get_bw_info(display, dram_info, &icl_sa_info);
+		icl_get_bw_info(display, dram_info, &icl_disp_bw_params);
 	}
 }
 

-- 
2.53.0

Re: [PATCH 3/4] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params

[Jani Nikula]

On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> To align with struct intel_platform_bw_params, rename struct
> intel_sa_info to intel_display_bw_params.  Also add comments to contrast
> their purposes.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 38 ++++++++++++++++++++-------------
>  1 file changed, 23 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 654876215ace..64c6f18346bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -375,6 +375,10 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>  	return dclk;
>  }
>  
> +/*
> + * Bandwidth parameters that are tied to the platform (as opposed to struct
> + * intel_display_bw_params).
> + */
>  struct intel_platform_bw_params {
>  	u8 deprogbwlimit;
>  	u8 derating;
> @@ -496,34 +500,38 @@ static const struct intel_platform_bw_params *get_platform_bw_params(struct inte
>  	return ret;
>  }
>  
> -struct intel_sa_info {
> +/*
> + * Bandwidth parameters that are tied to the display IP (as opposed to struct
> + * intel_platform_bw_params).
> + */
> +struct intel_display_bw_params {
>  	u16 displayrtids;
>  	u8 deburst;
>  };
>  
> -static const struct intel_sa_info icl_sa_info = {
> +static const struct intel_display_bw_params icl_disp_bw_params = {
>  	.deburst = 8,
>  	.displayrtids = 128,
>  };
>  
> -static const struct intel_sa_info tgl_sa_info = {
> +static const struct intel_display_bw_params tgl_disp_bw_params = {
>  	.deburst = 16,
>  	.displayrtids = 256,
>  };
>  
> -static const struct intel_sa_info rkl_sa_info = {
> +static const struct intel_display_bw_params rkl_disp_bw_params = {
>  	.deburst = 8,
>  	.displayrtids = 128,
>  };
>  
> -static const struct intel_sa_info xelpdp_sa_info = {
> +static const struct intel_display_bw_params xelpdp_disp_bw_params = {
>  	.deburst = 32,
>  	.displayrtids = 256,
>  };

So if these are tied to IP, why are they still named after platforms?

Nitpick, you'll never see me use "disp" abbreviation. It just doesn't
abbreviate enough, only makes stuff harder to read.

>  
>  static int icl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
> -			   const struct intel_sa_info *sa)
> +			   const struct intel_display_bw_params *disp_bw_params)
>  {
>  	struct intel_qgv_info qi = {};
>  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> @@ -544,7 +552,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  
>  	dclk_max = icl_sagv_max_dclk(&qi);
>  	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> +	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>  
>  	for (i = 0; i < num_groups; i++) {
> @@ -552,7 +560,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  		int clpchgroup;
>  		int j;
>  
> -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
> +		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
>  		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
>  
>  		bi->num_qgv_points = qi.num_points;
> @@ -595,7 +603,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  
>  static int tgl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
> -			   const struct intel_sa_info *sa)
> +			   const struct intel_display_bw_params *disp_bw_params)
>  {
>  	struct intel_qgv_info qi = {};
>  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> @@ -634,7 +642,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>  	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>  
> -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> +	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
>  	/*
>  	 * clperchgroup = 4kpagespermempage * clperchperblock,
>  	 * clperchperblock = 8 / num_channels * interleave
> @@ -647,7 +655,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  		int clpchgroup;
>  		int j;
>  
> -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
> +		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
>  
>  		if (i < num_groups - 1) {
>  			bi_next = &display->bw.max[i + 1];
> @@ -886,16 +894,16 @@ void intel_bw_init_hw(struct intel_display *display)
>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>  		xe2_hpd_get_bw_info(display, dram_info);
>  	} else if (DISPLAY_VER(display) >= 14) {
> -		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
> +		tgl_get_bw_info(display, dram_info, &xelpdp_disp_bw_params);
>  	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
>  	} else if (DISPLAY_VER(display) >= 12) {
>  		if (display->platform.rocketlake)
> -			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> +			tgl_get_bw_info(display, dram_info, &rkl_disp_bw_params);
>  		else
> -			tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> +			tgl_get_bw_info(display, dram_info, &tgl_disp_bw_params);
>  	} else if (DISPLAY_VER(display) == 11) {
> -		icl_get_bw_info(display, dram_info, &icl_sa_info);
> +		icl_get_bw_info(display, dram_info, &icl_disp_bw_params);
>  	}
>  }

-- 
Jani Nikula, Intel

Re: [PATCH 3/4] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params

[Gustavo Sousa]

Jani Nikula <jani.nikula@linux.intel.com> writes:

> On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> To align with struct intel_platform_bw_params, rename struct
>> intel_sa_info to intel_display_bw_params.  Also add comments to contrast
>> their purposes.
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 38 ++++++++++++++++++++-------------
>>  1 file changed, 23 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index 654876215ace..64c6f18346bb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -375,6 +375,10 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>>  	return dclk;
>>  }
>>  
>> +/*
>> + * Bandwidth parameters that are tied to the platform (as opposed to struct
>> + * intel_display_bw_params).
>> + */
>>  struct intel_platform_bw_params {
>>  	u8 deprogbwlimit;
>>  	u8 derating;
>> @@ -496,34 +500,38 @@ static const struct intel_platform_bw_params *get_platform_bw_params(struct inte
>>  	return ret;
>>  }
>>  
>> -struct intel_sa_info {
>> +/*
>> + * Bandwidth parameters that are tied to the display IP (as opposed to struct
>> + * intel_platform_bw_params).
>> + */
>> +struct intel_display_bw_params {
>>  	u16 displayrtids;
>>  	u8 deburst;
>>  };
>>  
>> -static const struct intel_sa_info icl_sa_info = {
>> +static const struct intel_display_bw_params icl_disp_bw_params = {
>>  	.deburst = 8,
>>  	.displayrtids = 128,
>>  };
>>  
>> -static const struct intel_sa_info tgl_sa_info = {
>> +static const struct intel_display_bw_params tgl_disp_bw_params = {
>>  	.deburst = 16,
>>  	.displayrtids = 256,
>>  };
>>  
>> -static const struct intel_sa_info rkl_sa_info = {
>> +static const struct intel_display_bw_params rkl_disp_bw_params = {
>>  	.deburst = 8,
>>  	.displayrtids = 128,
>>  };
>>  
>> -static const struct intel_sa_info xelpdp_sa_info = {
>> +static const struct intel_display_bw_params xelpdp_disp_bw_params = {
>>  	.deburst = 32,
>>  	.displayrtids = 256,
>>  };
>
> So if these are tied to IP, why are they still named after platforms?

Decided to use xelpdp for the one above and platform names for the other
ones because xelpdp is where we trully have IP disaggregation.

That said, I could try to use IP release names for the other ones as
well. So, something like below?

s/tgl_disp_bw_params/xe_d_bw_params/
s/rkl_disp_bw_params/xe_d_rkl_bw_params/
s/xelpdp_disp_bw_params/xe_lpdp_bw_params/

And what to do with icl_disp_bw_params? Do we have a suitable display
release name for it?

--
Gustavo Sousa

>
> Nitpick, you'll never see me use "disp" abbreviation. It just doesn't
> abbreviate enough, only makes stuff harder to read.
>
>>  
>>  static int icl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>> -			   const struct intel_sa_info *sa)
>> +			   const struct intel_display_bw_params *disp_bw_params)
>>  {
>>  	struct intel_qgv_info qi = {};
>>  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> @@ -544,7 +552,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  
>>  	dclk_max = icl_sagv_max_dclk(&qi);
>>  	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> +	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
>>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>>  
>>  	for (i = 0; i < num_groups; i++) {
>> @@ -552,7 +560,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  		int clpchgroup;
>>  		int j;
>>  
>> -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
>> +		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
>>  		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
>>  
>>  		bi->num_qgv_points = qi.num_points;
>> @@ -595,7 +603,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  
>>  static int tgl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>> -			   const struct intel_sa_info *sa)
>> +			   const struct intel_display_bw_params *disp_bw_params)
>>  {
>>  	struct intel_qgv_info qi = {};
>>  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
>> @@ -634,7 +642,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>>  	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>  
>> -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> +	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
>>  	/*
>>  	 * clperchgroup = 4kpagespermempage * clperchperblock,
>>  	 * clperchperblock = 8 / num_channels * interleave
>> @@ -647,7 +655,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  		int clpchgroup;
>>  		int j;
>>  
>> -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
>> +		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
>>  
>>  		if (i < num_groups - 1) {
>>  			bi_next = &display->bw.max[i + 1];
>> @@ -886,16 +894,16 @@ void intel_bw_init_hw(struct intel_display *display)
>>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>>  		xe2_hpd_get_bw_info(display, dram_info);
>>  	} else if (DISPLAY_VER(display) >= 14) {
>> -		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
>> +		tgl_get_bw_info(display, dram_info, &xelpdp_disp_bw_params);
>>  	} else if (display->platform.dg2) {
>>  		dg2_get_bw_info(display);
>>  	} else if (DISPLAY_VER(display) >= 12) {
>>  		if (display->platform.rocketlake)
>> -			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>> +			tgl_get_bw_info(display, dram_info, &rkl_disp_bw_params);
>>  		else
>> -			tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>> +			tgl_get_bw_info(display, dram_info, &tgl_disp_bw_params);
>>  	} else if (DISPLAY_VER(display) == 11) {
>> -		icl_get_bw_info(display, dram_info, &icl_sa_info);
>> +		icl_get_bw_info(display, dram_info, &icl_disp_bw_params);
>>  	}
>>  }
>
> -- 
> Jani Nikula, Intel

Re: [PATCH 3/4] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params

[Matt Roper]

On Wed, Apr 08, 2026 at 10:20:28PM +0300, Jani Nikula wrote:
> On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> > To align with struct intel_platform_bw_params, rename struct
> > intel_sa_info to intel_display_bw_params.  Also add comments to contrast
> > their purposes.
> >
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c | 38 ++++++++++++++++++++-------------
> >  1 file changed, 23 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 654876215ace..64c6f18346bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -375,6 +375,10 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
> >  	return dclk;
> >  }
> >  
> > +/*
> > + * Bandwidth parameters that are tied to the platform (as opposed to struct
> > + * intel_display_bw_params).
> > + */
> >  struct intel_platform_bw_params {
> >  	u8 deprogbwlimit;
> >  	u8 derating;
> > @@ -496,34 +500,38 @@ static const struct intel_platform_bw_params *get_platform_bw_params(struct inte
> >  	return ret;
> >  }
> >  
> > -struct intel_sa_info {
> > +/*
> > + * Bandwidth parameters that are tied to the display IP (as opposed to struct
> > + * intel_platform_bw_params).
> > + */
> > +struct intel_display_bw_params {
> >  	u16 displayrtids;
> >  	u8 deburst;
> >  };
> >  
> > -static const struct intel_sa_info icl_sa_info = {
> > +static const struct intel_display_bw_params icl_disp_bw_params = {
> >  	.deburst = 8,
> >  	.displayrtids = 128,
> >  };
> >  
> > -static const struct intel_sa_info tgl_sa_info = {
> > +static const struct intel_display_bw_params tgl_disp_bw_params = {
> >  	.deburst = 16,
> >  	.displayrtids = 256,
> >  };
> >  
> > -static const struct intel_sa_info rkl_sa_info = {
> > +static const struct intel_display_bw_params rkl_disp_bw_params = {
> >  	.deburst = 8,
> >  	.displayrtids = 128,
> >  };
> >  
> > -static const struct intel_sa_info xelpdp_sa_info = {
> > +static const struct intel_display_bw_params xelpdp_disp_bw_params = {
> >  	.deburst = 32,
> >  	.displayrtids = 256,
> >  };
> 
> So if these are tied to IP, why are they still named after platforms?

Although we're not allowed to use "gen" terminology with newer IPs,
"gen12" and earlier are grandfathered in and still okay to use since
they existed and were in widespread public use when the new rules came
down.  So we should use gen11 and gen12 in place of ICL and TGL here.

As noted on the previous patch, RKL was a weird exception to all the
rules and I'd be okay explicitly forcing it to use the "gen11"
structures even though it's officially got IP version 12 since it kind
of makes sense from how they frankensteined that platform together at
the hardware level.


Matt

> 
> Nitpick, you'll never see me use "disp" abbreviation. It just doesn't
> abbreviate enough, only makes stuff harder to read.
> 
> >  
> >  static int icl_get_bw_info(struct intel_display *display,
> >  			   const struct dram_info *dram_info,
> > -			   const struct intel_sa_info *sa)
> > +			   const struct intel_display_bw_params *disp_bw_params)
> >  {
> >  	struct intel_qgv_info qi = {};
> >  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> > @@ -544,7 +552,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >  
> >  	dclk_max = icl_sagv_max_dclk(&qi);
> >  	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> > -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> > +	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
> >  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
> >  
> >  	for (i = 0; i < num_groups; i++) {
> > @@ -552,7 +560,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >  		int clpchgroup;
> >  		int j;
> >  
> > -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
> > +		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
> >  		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
> >  
> >  		bi->num_qgv_points = qi.num_points;
> > @@ -595,7 +603,7 @@ static int icl_get_bw_info(struct intel_display *display,
> >  
> >  static int tgl_get_bw_info(struct intel_display *display,
> >  			   const struct dram_info *dram_info,
> > -			   const struct intel_sa_info *sa)
> > +			   const struct intel_display_bw_params *disp_bw_params)
> >  {
> >  	struct intel_qgv_info qi = {};
> >  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> > @@ -634,7 +642,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
> >  	maxdebw = min(plat_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> >  
> > -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> > +	ipqdepth = min(ipqdepthpch, disp_bw_params->displayrtids / num_channels);
> >  	/*
> >  	 * clperchgroup = 4kpagespermempage * clperchperblock,
> >  	 * clperchperblock = 8 / num_channels * interleave
> > @@ -647,7 +655,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> >  		int clpchgroup;
> >  		int j;
> >  
> > -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
> > +		clpchgroup = (disp_bw_params->deburst * qi.deinterleave / num_channels) << i;
> >  
> >  		if (i < num_groups - 1) {
> >  			bi_next = &display->bw.max[i + 1];
> > @@ -886,16 +894,16 @@ void intel_bw_init_hw(struct intel_display *display)
> >  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> >  		xe2_hpd_get_bw_info(display, dram_info);
> >  	} else if (DISPLAY_VER(display) >= 14) {
> > -		tgl_get_bw_info(display, dram_info, &xelpdp_sa_info);
> > +		tgl_get_bw_info(display, dram_info, &xelpdp_disp_bw_params);
> >  	} else if (display->platform.dg2) {
> >  		dg2_get_bw_info(display);
> >  	} else if (DISPLAY_VER(display) >= 12) {
> >  		if (display->platform.rocketlake)
> > -			tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> > +			tgl_get_bw_info(display, dram_info, &rkl_disp_bw_params);
> >  		else
> > -			tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> > +			tgl_get_bw_info(display, dram_info, &tgl_disp_bw_params);
> >  	} else if (DISPLAY_VER(display) == 11) {
> > -		icl_get_bw_info(display, dram_info, &icl_sa_info);
> > +		icl_get_bw_info(display, dram_info, &icl_disp_bw_params);
> >  	}
> >  }
> 
> -- 
> Jani Nikula, Intel

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH 4/4] drm/i915/bw: Extract get_display_bw_params()

[Gustavo Sousa]

Just like it is done for the platform-specific bandwidth parameters, use
a separate function named get_display_bw_params() to return the display
IP-specific parameters.  This simplifies intel_bw_init_hw() by having
just one call for each of *_get_info() function.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 64c6f18346bb..1f08fb893ee7 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -529,12 +529,26 @@ static const struct intel_display_bw_params xelpdp_disp_bw_params = {
 	.displayrtids = 256,
 };
 
+static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
+{
+	if (DISPLAY_VER(display) >= 14) {
+		return &xelpdp_disp_bw_params;
+	} else if (DISPLAY_VER(display) >= 12) {
+		if (display->platform.rocketlake)
+			return &rkl_disp_bw_params;
+		else
+			return &tgl_disp_bw_params;
+	} else {
+		return &icl_disp_bw_params;
+	}
+}
+
 static int icl_get_bw_info(struct intel_display *display,
-			   const struct dram_info *dram_info,
-			   const struct intel_display_bw_params *disp_bw_params)
+			   const struct dram_info *dram_info)
 {
 	struct intel_qgv_info qi = {};
 	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
+	const struct intel_display_bw_params *disp_bw_params = get_display_bw_params(display);
 	bool is_y_tile = true; /* assume y tile may be used */
 	int num_channels = max_t(u8, 1, dram_info->num_channels);
 	int ipqdepth, ipqdepthpch = 16;
@@ -602,11 +616,11 @@ static int icl_get_bw_info(struct intel_display *display,
 }
 
 static int tgl_get_bw_info(struct intel_display *display,
-			   const struct dram_info *dram_info,
-			   const struct intel_display_bw_params *disp_bw_params)
+			   const struct dram_info *dram_info)
 {
 	struct intel_qgv_info qi = {};
 	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
+	const struct intel_display_bw_params *disp_bw_params = get_display_bw_params(display);
 	bool is_y_tile = true; /* assume y tile may be used */
 	int num_channels = max_t(u8, 1, dram_info->num_channels);
 	int ipqdepth, ipqdepthpch = 16;
@@ -893,17 +907,12 @@ void intel_bw_init_hw(struct intel_display *display)
 
 	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
 		xe2_hpd_get_bw_info(display, dram_info);
-	} else if (DISPLAY_VER(display) >= 14) {
-		tgl_get_bw_info(display, dram_info, &xelpdp_disp_bw_params);
 	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
 	} else if (DISPLAY_VER(display) >= 12) {
-		if (display->platform.rocketlake)
-			tgl_get_bw_info(display, dram_info, &rkl_disp_bw_params);
-		else
-			tgl_get_bw_info(display, dram_info, &tgl_disp_bw_params);
+		tgl_get_bw_info(display, dram_info);
 	} else if (DISPLAY_VER(display) == 11) {
-		icl_get_bw_info(display, dram_info, &icl_disp_bw_params);
+		icl_get_bw_info(display, dram_info);
 	}
 }
 

-- 
2.53.0

Re: [PATCH 4/4] drm/i915/bw: Extract get_display_bw_params()

[Jani Nikula]

On Wed, 08 Apr 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Just like it is done for the platform-specific bandwidth parameters, use
> a separate function named get_display_bw_params() to return the display
> IP-specific parameters.  This simplifies intel_bw_init_hw() by having
> just one call for each of *_get_info() function.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 31 ++++++++++++++++++++-----------
>  1 file changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 64c6f18346bb..1f08fb893ee7 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -529,12 +529,26 @@ static const struct intel_display_bw_params xelpdp_disp_bw_params = {
>  	.displayrtids = 256,
>  };
>  
> +static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
> +{
> +	if (DISPLAY_VER(display) >= 14) {
> +		return &xelpdp_disp_bw_params;
> +	} else if (DISPLAY_VER(display) >= 12) {
> +		if (display->platform.rocketlake)
> +			return &rkl_disp_bw_params;
> +		else
> +			return &tgl_disp_bw_params;
> +	} else {
> +		return &icl_disp_bw_params;
> +	}
> +}
> +
>  static int icl_get_bw_info(struct intel_display *display,
> -			   const struct dram_info *dram_info,
> -			   const struct intel_display_bw_params *disp_bw_params)
> +			   const struct dram_info *dram_info)
>  {
>  	struct intel_qgv_info qi = {};
>  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> +	const struct intel_display_bw_params *disp_bw_params = get_display_bw_params(display);

I would pass both of these in as parameters, with centralized
assignment, and not have every single function call the getters.

>  	bool is_y_tile = true; /* assume y tile may be used */
>  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>  	int ipqdepth, ipqdepthpch = 16;
> @@ -602,11 +616,11 @@ static int icl_get_bw_info(struct intel_display *display,
>  }
>  
>  static int tgl_get_bw_info(struct intel_display *display,
> -			   const struct dram_info *dram_info,
> -			   const struct intel_display_bw_params *disp_bw_params)
> +			   const struct dram_info *dram_info)
>  {
>  	struct intel_qgv_info qi = {};
>  	const struct intel_platform_bw_params *plat_bw_params = get_platform_bw_params(display);
> +	const struct intel_display_bw_params *disp_bw_params = get_display_bw_params(display);
>  	bool is_y_tile = true; /* assume y tile may be used */
>  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>  	int ipqdepth, ipqdepthpch = 16;
> @@ -893,17 +907,12 @@ void intel_bw_init_hw(struct intel_display *display)
>  
>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>  		xe2_hpd_get_bw_info(display, dram_info);
> -	} else if (DISPLAY_VER(display) >= 14) {
> -		tgl_get_bw_info(display, dram_info, &xelpdp_disp_bw_params);
>  	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
>  	} else if (DISPLAY_VER(display) >= 12) {
> -		if (display->platform.rocketlake)
> -			tgl_get_bw_info(display, dram_info, &rkl_disp_bw_params);
> -		else
> -			tgl_get_bw_info(display, dram_info, &tgl_disp_bw_params);
> +		tgl_get_bw_info(display, dram_info);
>  	} else if (DISPLAY_VER(display) == 11) {
> -		icl_get_bw_info(display, dram_info, &icl_disp_bw_params);
> +		icl_get_bw_info(display, dram_info);
>  	}
>  }

-- 
Jani Nikula, Intel

✓ i915.CI.BAT: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1921 bytes --]

== Series Details ==

Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs
URL   : https://patchwork.freedesktop.org/series/164567/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18295 -> Patchwork_164567v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_164567v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-dg2-8:          [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/bat-dg2-8/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/bat-dg2-8/igt@i915_selftest@live.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [DMESG-FAIL][3] ([i915#12061]) -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/bat-mtlp-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/bat-mtlp-8/igt@i915_selftest@live.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_18295 -> Patchwork_164567v1

  CI-20190529: 20190529
  CI_DRM_18295: 08037efa91c349ee17b62ddd1908a846d7abd917 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8850: 8850
  Patchwork_164567v1: 08037efa91c349ee17b62ddd1908a846d7abd917 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/index.html

[-- Attachment #2: Type: text/html, Size: 2609 bytes --]

✓ i915.CI.Full: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 127947 bytes --]

== Series Details ==

Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs
URL   : https://patchwork.freedesktop.org/series/164567/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18295_full -> Patchwork_164567v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_164567v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg2:          NOTRUN -> [SKIP][1] ([i915#8411])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@crc32:
    - shard-rkl:          NOTRUN -> [SKIP][2] ([i915#6230])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@api_intel_bb@crc32.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          NOTRUN -> [SKIP][3] ([i915#11078]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          NOTRUN -> [SKIP][4] ([i915#9323])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#3555] / [i915#9323])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [PASS][6] -> [INCOMPLETE][7] ([i915#13356]) +1 other test incomplete
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-4/igt@gem_ccs@suspend-resume.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_ccs@suspend-resume.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg2:          NOTRUN -> [SKIP][8] ([i915#7697])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-tglu-1:       NOTRUN -> [SKIP][9] ([i915#7697])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-set-pat:
    - shard-tglu-1:       NOTRUN -> [SKIP][10] ([i915#8562])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-glk:          NOTRUN -> [INCOMPLETE][11] ([i915#13356])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk4/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt:
    - shard-dg2:          NOTRUN -> [SKIP][12] ([i915#5882]) +7 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@gem_ctx_persistence@saturated-hostile-nopreempt.html

  * igt@gem_ctx_sseu@engines:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#280])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_ctx_sseu@engines.html
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#280])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-tglu:         NOTRUN -> [SKIP][15] ([i915#280])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_eio@hibernate:
    - shard-rkl:          [PASS][16] -> [ABORT][17] ([i915#7975])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-8/igt@gem_eio@hibernate.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-1/igt@gem_eio@hibernate.html

  * igt@gem_eio@kms:
    - shard-tglu:         NOTRUN -> [ABORT][18] ([i915#13363])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-4/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#4525]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_capture@capture@vecs0-lmem0:
    - shard-dg2:          NOTRUN -> [FAIL][20] ([i915#11965]) +4 other tests fail
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_exec_capture@capture@vecs0-lmem0.html

  * igt@gem_exec_fence@submit67:
    - shard-dg1:          NOTRUN -> [SKIP][21] ([i915#4812])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_exec_fence@submit67.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg1:          NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#3539] / [i915#4852]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_reloc@basic-concurrent16:
    - shard-dg1:          NOTRUN -> [SKIP][24] ([i915#3281]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_exec_reloc@basic-concurrent16.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#3281]) +11 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#3281]) +5 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-rkl:          NOTRUN -> [SKIP][27] ([i915#7276])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_exec_suspend@basic-s3-devices:
    - shard-dg2:          [PASS][28] -> [ABORT][29] ([i915#15131]) +1 other test abort
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-4/igt@gem_exec_suspend@basic-s3-devices.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@gem_exec_suspend@basic-s3-devices.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#4860]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#4613] / [i915#7582])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-glk:          NOTRUN -> [SKIP][32] ([i915#4613])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk8/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-tglu:         NOTRUN -> [SKIP][33] ([i915#4613]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][34] ([i915#4613]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gem_lmem_swapping@verify-random-ccs.html
    - shard-rkl:          NOTRUN -> [SKIP][35] ([i915#4613])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_madvise@dontneed-before-pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#3282]) +4 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@gem_madvise@dontneed-before-pwrite.html

  * igt@gem_media_vme:
    - shard-tglu-1:       NOTRUN -> [SKIP][37] ([i915#284])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gem_media_vme.html

  * igt@gem_mmap@bad-offset:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#4083]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@gem_mmap@bad-offset.html

  * igt@gem_mmap@short-mmap:
    - shard-dg1:          NOTRUN -> [SKIP][39] ([i915#4083]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_mmap@short-mmap.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-xy:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([i915#4077]) +5 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html

  * igt@gem_mmap_gtt@zero-extend:
    - shard-dg1:          NOTRUN -> [SKIP][41] ([i915#4077]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_mmap_gtt@zero-extend.html

  * igt@gem_pread@exhaustion:
    - shard-tglu-1:       NOTRUN -> [WARN][42] ([i915#2658])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-dg1:          NOTRUN -> [SKIP][43] ([i915#3282]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
    - shard-dg1:          NOTRUN -> [SKIP][44] ([i915#4270])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#4270]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_readwrite@write-bad-handle:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#3282]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_readwrite@write-bad-handle.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([i915#5190] / [i915#8428]) +3 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4079])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#8411]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_unfence_active_buffers:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#4879])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][51] ([i915#3297]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html
    - shard-tglu-1:       NOTRUN -> [SKIP][52] ([i915#3297]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#3297])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@sd-probe:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#3297] / [i915#4958])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@gem_userptr_blits@sd-probe.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-tglu:         NOTRUN -> [SKIP][55] ([i915#3297])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gem_workarounds@suspend-resume:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][56] ([i915#13356]) +1 other test incomplete
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-4/igt@gem_workarounds@suspend-resume.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-rkl:          [PASS][57] -> [INCOMPLETE][58] ([i915#13356])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gem_workarounds@suspend-resume-fd.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_workarounds@suspend-resume-fd.html
    - shard-glk11:        NOTRUN -> [INCOMPLETE][59] ([i915#13356] / [i915#14586])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk11/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@batch-without-end:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#2527])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@gen9_exec_parse@batch-without-end.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#2856]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@gen9_exec_parse@bb-start-out.html
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#2527]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@gen9_exec_parse@bb-start-out.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-tglu:         NOTRUN -> [SKIP][63] ([i915#2527] / [i915#2856])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@gen9_exec_parse@secure-batches.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-tglu-1:       NOTRUN -> [SKIP][64] ([i915#2527] / [i915#2856]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_drm_fdinfo@busy-check-all@vecs0:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#11527]) +7 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@i915_drm_fdinfo@busy-check-all@vecs0.html

  * igt@i915_drm_fdinfo@most-busy-check-all@vcs1:
    - shard-dg1:          NOTRUN -> [SKIP][66] ([i915#14073]) +5 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@i915_drm_fdinfo@most-busy-check-all@vcs1.html

  * igt@i915_module_load@fault-injection:
    - shard-dg1:          NOTRUN -> [ABORT][67] ([i915#15481]) +1 other test abort
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@i915_module_load@fault-injection.html

  * igt@i915_module_load@fault-injection@i915_driver_mmio_probe:
    - shard-dg1:          NOTRUN -> [INCOMPLETE][68] ([i915#15481])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@i915_module_load@fault-injection@i915_driver_mmio_probe.html

  * igt@i915_module_load@reload-no-display:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][69] ([i915#13029] / [i915#14545])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#8399]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglu-1:       NOTRUN -> [SKIP][71] ([i915#4387])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@hwconfig_table:
    - shard-tglu:         NOTRUN -> [SKIP][72] ([i915#6245])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-4/igt@i915_query@hwconfig_table.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][73] ([i915#5723])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-rkl:          [PASS][74] -> [INCOMPLETE][75] ([i915#4817])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@i915_suspend@fence-restore-tiled2untiled.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@i915_suspend@sysfs-reader:
    - shard-glk:          [PASS][76] -> [INCOMPLETE][77] ([i915#4817])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-glk1/igt@i915_suspend@sysfs-reader.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk8/igt@i915_suspend@sysfs-reader.html

  * igt@intel_hwmon@hwmon-write:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#7707])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@intel_hwmon@hwmon-write.html
    - shard-tglu-1:       NOTRUN -> [SKIP][79] ([i915#7707])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#4212]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#12454] / [i915#12712])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-rkl:          [PASS][82] -> [INCOMPLETE][83] ([i915#12761]) +1 other test incomplete
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@kms_async_flips@async-flip-suspend-resume.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_async_flips@async-flip-suspend-resume.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][84] ([i915#12761]) +1 other test incomplete
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk8/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#9531])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          [PASS][86] -> [FAIL][87] ([i915#5956]) +1 other test fail
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][88] ([i915#5286]) +2 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][89] ([i915#4538] / [i915#5286])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#5286]) +4 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][91] ([i915#5286]) +5 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][92] ([i915#3638]) +2 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#3828])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#3828])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
    - shard-tglu-1:       NOTRUN -> [SKIP][95] ([i915#3828])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][96] +7 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#4538] / [i915#5190]) +4 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][98] +40 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#6095]) +35 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#14098] / [i915#6095]) +45 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][101] ([i915#12313]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][102] ([i915#12313] / [i915#4423])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][103] ([i915#12313])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][104] ([i915#14098] / [i915#14544] / [i915#6095]) +5 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][105] ([i915#6095]) +39 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [PASS][106] -> [INCOMPLETE][107] ([i915#15582]) +1 other test incomplete
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][108] ([i915#6095]) +59 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][109] ([i915#12313]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#14544] / [i915#6095]) +10 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][111] ([i915#6095]) +68 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#10307] / [i915#6095]) +73 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#6095]) +181 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-tglu:         NOTRUN -> [SKIP][114] ([i915#11151] / [i915#7828]) +5 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@degamma:
    - shard-rkl:          NOTRUN -> [SKIP][115] +21 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-tglu-1:       NOTRUN -> [SKIP][116] ([i915#11151] / [i915#7828]) +4 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#11151] / [i915#7828]) +6 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#11151] / [i915#7828]) +7 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#11151] / [i915#7828])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_color@deep-color:
    - shard-tglu-1:       NOTRUN -> [SKIP][120] ([i915#3555] / [i915#9979])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_color@deep-color.html

  * igt@kms_color@legacy-gamma-reset:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][121] ([i915#4423]) +5 other tests dmesg-warn
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_color@legacy-gamma-reset.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#15865]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#15330] / [i915#3116])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_content_protection@dp-mst-lic-type-0.html
    - shard-tglu-1:       NOTRUN -> [SKIP][124] ([i915#15330] / [i915#3116] / [i915#3299])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg1:          NOTRUN -> [SKIP][125] ([i915#15330] / [i915#3299] / [i915#4423])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-glk11:        NOTRUN -> [SKIP][126] +69 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk11/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#15865]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#15865]) +2 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][129] ([i915#7173])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@kms_content_protection@suspend-resume@pipe-a-dp-3.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-tglu-1:       NOTRUN -> [SKIP][130] ([i915#15865]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][131] ([i915#3555]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#13049]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][133] ([i915#13049])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][134] -> [FAIL][135] ([i915#13566]) +1 other test fail
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-tglu-10/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-10/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][136] ([i915#13566])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][137] ([i915#13049]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][138] ([i915#3555]) +2 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-tglu:         NOTRUN -> [SKIP][139] ([i915#3555]) +3 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-tglu-1:       NOTRUN -> [FAIL][140] ([i915#13566]) +1 other test fail
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#13049]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][142] ([i915#13049] / [i915#4423])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][143] ([i915#4103] / [i915#4213])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#4103])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#13046] / [i915#5354]) +2 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-tglu:         NOTRUN -> [SKIP][146] ([i915#9067])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-4/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][147] ([i915#9723])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-tglu:         NOTRUN -> [SKIP][148] ([i915#1769] / [i915#3555] / [i915#3804])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][149] ([i915#3804])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#3555]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-dg1:          NOTRUN -> [SKIP][151] ([i915#13748])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-tglu-1:       NOTRUN -> [SKIP][152] ([i915#13707])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-tglu:         NOTRUN -> [SKIP][153] ([i915#3555] / [i915#3840])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#3840])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-dg2:          NOTRUN -> [SKIP][155] ([i915#3555] / [i915#3840])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-tglu:         NOTRUN -> [SKIP][156] ([i915#3840] / [i915#9053])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2:          NOTRUN -> [SKIP][157] ([i915#9337])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_feature_discovery@dp-mst.html
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#9337])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-tglu:         NOTRUN -> [SKIP][159] ([i915#3637] / [i915#9934]) +2 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-tglu-1:       NOTRUN -> [SKIP][160] ([i915#9934])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][161] ([i915#9934]) +2 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_flip@2x-flip-vs-panning-interruptible.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-dg1:          NOTRUN -> [SKIP][162] ([i915#9934]) +2 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-rkl:          NOTRUN -> [SKIP][163] ([i915#9934]) +6 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][164] ([i915#3637] / [i915#9934]) +6 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][165] ([i915#12745] / [i915#4839] / [i915#6113])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][166] ([i915#12745])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk3/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#15643]) +2 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][168] ([i915#15643])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
    - shard-dg1:          NOTRUN -> [SKIP][169] ([i915#15643])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][170] ([i915#15643]) +2 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][171] ([i915#15643]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_force_connector_basic@force-edid:
    - shard-mtlp:         [PASS][172] -> [SKIP][173] ([i915#15672]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-mtlp-3/igt@kms_force_connector_basic@force-edid.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-mtlp-1/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][174] ([i915#8708]) +9 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move:
    - shard-tglu:         NOTRUN -> [SKIP][175] +29 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][176] ([i915#5439])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#15102]) +2 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][178] ([i915#8708]) +3 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt:
    - shard-dg1:          NOTRUN -> [SKIP][179] ([i915#4423]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
    - shard-tglu:         NOTRUN -> [SKIP][180] ([i915#15102]) +16 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
    - shard-dg2:          NOTRUN -> [SKIP][181] ([i915#15102] / [i915#3458]) +6 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#10055])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][183] ([i915#15102])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][184] ([i915#15104]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][185] ([i915#15102]) +3 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
    - shard-glk:          NOTRUN -> [SKIP][186] +75 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk8/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][187] ([i915#15102]) +14 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-dg2:          NOTRUN -> [SKIP][188] ([i915#10433] / [i915#15102] / [i915#3458])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#15102] / [i915#3023]) +24 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg1:          NOTRUN -> [SKIP][190] ([i915#15102] / [i915#3458]) +2 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#1825]) +24 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#5354]) +20 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][193] +3 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-tglu:         NOTRUN -> [SKIP][194] ([i915#13030])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          NOTRUN -> [SKIP][195] ([i915#12713])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-rkl:          NOTRUN -> [SKIP][196] ([i915#3555] / [i915#8228])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_hdr@static-toggle.html
    - shard-tglu-1:       NOTRUN -> [SKIP][197] ([i915#3555] / [i915#8228])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][198] ([i915#3555] / [i915#8228]) +1 other test skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][199] ([i915#15459])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][200] ([i915#15458])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][201] ([i915#13688])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][202] ([i915#15459]) +1 other test skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][203] ([i915#15458])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][204] ([i915#15638] / [i915#15722])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2:
    - shard-rkl:          [PASS][205] -> [INCOMPLETE][206] ([i915#13476])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-3/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-dg2:          NOTRUN -> [SKIP][207] ([i915#14712])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
    - shard-rkl:          NOTRUN -> [SKIP][208] ([i915#14712])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2:          NOTRUN -> [SKIP][209] ([i915#13705])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier-source-clamping:
    - shard-dg2:          NOTRUN -> [SKIP][210] ([i915#15709]) +2 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#15709]) +4 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
    - shard-tglu-1:       NOTRUN -> [SKIP][212] ([i915#15709]) +1 other test skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier@pipe-b-plane-7:
    - shard-tglu-1:       NOTRUN -> [SKIP][213] ([i915#15608]) +1 other test skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier@pipe-b-plane-7.html

  * igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][214] ([i915#15608]) +1 other test skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
    - shard-tglu:         NOTRUN -> [SKIP][215] ([i915#15709]) +2 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][216] ([i915#10647] / [i915#12169])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk8/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][217] ([i915#10647]) +1 other test fail
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk8/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-dg1:          NOTRUN -> [SKIP][218] ([i915#13958])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          NOTRUN -> [SKIP][219] ([i915#13958])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_plane_multiple@2x-tiling-none.html
    - shard-tglu-1:       NOTRUN -> [SKIP][220] ([i915#13958])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][221] ([i915#14259])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-4/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-dg2:          NOTRUN -> [SKIP][222] ([i915#13046] / [i915#5354] / [i915#9423])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b:
    - shard-rkl:          NOTRUN -> [SKIP][223] ([i915#15329]) +7 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d:
    - shard-tglu-1:       NOTRUN -> [SKIP][224] ([i915#15329]) +4 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2:          NOTRUN -> [SKIP][225] ([i915#3828])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-dg2:          NOTRUN -> [SKIP][226] ([i915#9685])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_pm_dc@dc6-psr.html
    - shard-rkl:          NOTRUN -> [SKIP][227] ([i915#9685])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-7/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][228] ([i915#15739])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          [PASS][229] -> [SKIP][230] ([i915#15073]) +1 other test skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#15073]) +1 other test skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#6524])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-tglu:         NOTRUN -> [SKIP][233] ([i915#6524])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-4/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg2:          NOTRUN -> [SKIP][234] ([i915#6524] / [i915#6805]) +1 other test skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_prime@d3hot.html

  * igt@kms_properties@get_properties-sanity-atomic:
    - shard-dg1:          [PASS][235] -> [DMESG-WARN][236] ([i915#4423]) +3 other tests dmesg-warn
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-14/igt@kms_properties@get_properties-sanity-atomic.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-15/igt@kms_properties@get_properties-sanity-atomic.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][237] ([i915#11520]) +6 other tests skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
    - shard-tglu-1:       NOTRUN -> [SKIP][238] ([i915#11520]) +4 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][239] ([i915#11520]) +5 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-glk11:        NOTRUN -> [SKIP][240] ([i915#11520]) +2 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk11/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][241] ([i915#11520]) +1 other test skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][242] ([i915#11520]) +6 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][243] ([i915#11520]) +1 other test skip
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk8/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2:          NOTRUN -> [SKIP][244] ([i915#9683])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-tglu:         NOTRUN -> [SKIP][245] ([i915#9683])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr-basic:
    - shard-dg2:          NOTRUN -> [SKIP][246] ([i915#1072] / [i915#9732]) +12 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_psr@fbc-psr-basic.html

  * igt@kms_psr@fbc-psr2-cursor-blt:
    - shard-tglu:         NOTRUN -> [SKIP][247] ([i915#9732]) +12 other tests skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@kms_psr@fbc-psr2-cursor-blt.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-tglu-1:       NOTRUN -> [SKIP][248] ([i915#9732]) +17 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@pr-cursor-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][249] ([i915#1072] / [i915#4423] / [i915#9732])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_psr@pr-cursor-mmap-gtt.html

  * igt@kms_psr@psr-cursor-plane-move:
    - shard-dg1:          NOTRUN -> [SKIP][250] ([i915#1072] / [i915#9732]) +1 other test skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_psr@psr-cursor-plane-move.html

  * igt@kms_psr@psr2-cursor-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][251] ([i915#1072] / [i915#9732]) +22 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_psr@psr2-cursor-mmap-gtt.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-dg1:          NOTRUN -> [SKIP][252] ([i915#5289])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-dg2:          NOTRUN -> [SKIP][253] ([i915#12755] / [i915#15867] / [i915#5190])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][254] ([i915#5289]) +1 other test skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-rkl:          NOTRUN -> [SKIP][255] ([i915#5289])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2:          NOTRUN -> [SKIP][256] ([i915#12755] / [i915#15867]) +1 other test skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
    - shard-dg2:          NOTRUN -> [ABORT][257] ([i915#13179]) +1 other test abort
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-1:
    - shard-rkl:          [PASS][258] -> [FAIL][259] ([i915#15106]) +2 other tests fail
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-5/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
    - shard-dg1:          NOTRUN -> [FAIL][260] ([i915#15106]) +1 other test fail
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-14/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html

  * igt@kms_setmode@basic@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][261] ([i915#15106]) +2 other tests fail
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_setmode@basic@pipe-b-hdmi-a-3.html

  * igt@kms_vrr@flip-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][262] ([i915#15243] / [i915#3555])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@negative-basic:
    - shard-rkl:          NOTRUN -> [SKIP][263] ([i915#3555] / [i915#9906])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][264] ([i915#9906]) +1 other test skip
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-dg2:          NOTRUN -> [SKIP][265] ([i915#9906])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-tglu:         NOTRUN -> [SKIP][266] ([i915#8516])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-7/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@basic-fence-flip:
    - shard-dg2:          NOTRUN -> [SKIP][267] ([i915#3708])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-5/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-dg1:          NOTRUN -> [SKIP][268] ([i915#3708]) +1 other test skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@prime_vgem@fence-flip-hang.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-rkl:          NOTRUN -> [SKIP][269] ([i915#9917])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-dg1:          NOTRUN -> [SKIP][270] ([i915#9917])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-12/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-glk:          [INCOMPLETE][271] ([i915#13356]) -> [PASS][272]
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-glk8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk4/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [INCOMPLETE][273] ([i915#13356]) -> [PASS][274] +1 other test pass
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-5/igt@gem_exec_suspend@basic-s0.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglu:         [WARN][275] ([i915#13790] / [i915#2681]) -> [PASS][276] +1 other test pass
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-fence.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-6/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-dg2:          [DMESG-WARN][277] ([i915#13562]) -> [PASS][278]
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-5/igt@i915_pm_rpm@system-suspend-execbuf.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-4/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [INCOMPLETE][279] ([i915#4817]) -> [PASS][280]
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@i915_suspend@forcewake.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@i915_suspend@forcewake.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-dg1:          [FAIL][281] ([i915#5956]) -> [PASS][282]
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-15/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-13/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-mtlp:         [FAIL][283] ([i915#5956]) -> [PASS][284] +1 other test pass
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-mtlp-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-mtlp-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_cursor_crc@cursor-random-64x21:
    - shard-rkl:          [FAIL][285] ([i915#13566]) -> [PASS][286] +2 other tests pass
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_cursor_crc@cursor-random-64x21.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-5/igt@kms_cursor_crc@cursor-random-64x21.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-2:
    - shard-rkl:          [INCOMPLETE][287] ([i915#12358] / [i915#14152]) -> [PASS][288] +1 other test pass
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-2.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-dg2:          [FAIL][289] ([i915#13027]) -> [PASS][290]
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a3:
    - shard-dg2:          [FAIL][291] ([i915#15718]) -> [PASS][292]
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a3.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a3.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-dg2:          [SKIP][293] ([i915#3555] / [i915#8228]) -> [PASS][294]
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-3/igt@kms_hdr@bpc-switch-suspend.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][295] ([i915#14544] / [i915#15073]) -> [PASS][296]
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg1:          [SKIP][297] ([i915#15073]) -> [PASS][298] +1 other test pass
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-18/igt@kms_pm_rpm@modeset-lpsp.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-14/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][299] ([i915#15073]) -> [PASS][300] +1 other test pass
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-dg2:          [INCOMPLETE][301] ([i915#14419]) -> [PASS][302]
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-5/igt@kms_pm_rpm@system-suspend-idle.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-8/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_setmode@basic:
    - shard-tglu:         [FAIL][303] ([i915#15106]) -> [PASS][304] +2 other tests pass
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-tglu-7/igt@kms_setmode@basic.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-tglu-5/igt@kms_setmode@basic.html

  * igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1:
    - shard-snb:          [FAIL][305] ([i915#15106]) -> [PASS][306] +1 other test pass
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-snb6/igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-snb6/igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-rkl:          [INCOMPLETE][307] ([i915#12276]) -> [PASS][308]
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vrr@negative-basic:
    - shard-mtlp:         [FAIL][309] ([i915#15420]) -> [PASS][310] +1 other test pass
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-mtlp-1/igt@kms_vrr@negative-basic.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-mtlp-7/igt@kms_vrr@negative-basic.html

  
#### Warnings ####

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          [SKIP][311] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][312] ([i915#3555] / [i915#9323])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_ccs@ctrl-surf-copy.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][313] ([i915#13008]) -> [SKIP][314] ([i915#13008] / [i915#14544])
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gem_ccs@large-ctrl-surf-copy.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-rkl:          [SKIP][315] ([i915#6335]) -> [SKIP][316] ([i915#14544] / [i915#6335])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gem_create@create-ext-cpu-access-big.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-set-pat:
    - shard-rkl:          [SKIP][317] ([i915#14544] / [i915#8562]) -> [SKIP][318] ([i915#8562])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_create@create-ext-set-pat.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@gem_create@create-ext-set-pat.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][319] ([i915#4525]) -> [SKIP][320] ([i915#14544] / [i915#4525]) +1 other test skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gem_exec_balancer@parallel.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-rkl:          [SKIP][321] ([i915#14544] / [i915#4525]) -> [SKIP][322] ([i915#4525])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_exec_balancer@parallel-contexts.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          [SKIP][323] ([i915#6344]) -> [SKIP][324] ([i915#14544] / [i915#6344])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gem_exec_capture@capture-recoverable.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-rkl:          [SKIP][325] -> [SKIP][326] ([i915#14544]) +8 other tests skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_nop@basic-parallel:
    - shard-mtlp:         [ABORT][327] -> [ABORT][328] ([i915#13562])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-mtlp-8/igt@gem_exec_nop@basic-parallel.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-mtlp-5/igt@gem_exec_nop@basic-parallel.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-rkl:          [SKIP][329] ([i915#14544] / [i915#3281]) -> [SKIP][330] ([i915#3281]) +4 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_exec_reloc@basic-write-wc-noreloc:
    - shard-rkl:          [SKIP][331] ([i915#3281]) -> [SKIP][332] ([i915#14544] / [i915#3281]) +5 other tests skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@gem_exec_reloc@basic-write-wc-noreloc.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_exec_reloc@basic-write-wc-noreloc.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-rkl:          [SKIP][333] ([i915#14544] / [i915#4613]) -> [SKIP][334] ([i915#4613])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-rkl:          [SKIP][335] ([i915#4613]) -> [SKIP][336] ([i915#14544] / [i915#4613]) +3 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@gem_lmem_swapping@random-engines.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_media_vme:
    - shard-rkl:          [SKIP][337] ([i915#14544] / [i915#284]) -> [SKIP][338] ([i915#284])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_media_vme.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@gem_media_vme.html

  * igt@gem_pread@snoop:
    - shard-rkl:          [SKIP][339] ([i915#14544] / [i915#3282]) -> [SKIP][340] ([i915#3282]) +1 other test skip
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_pread@snoop.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@gem_pread@snoop.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-rkl:          [SKIP][341] ([i915#3282]) -> [SKIP][342] ([i915#14544] / [i915#3282])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-rkl:          [SKIP][343] ([i915#14544] / [i915#3282] / [i915#3297]) -> [SKIP][344] ([i915#3282] / [i915#3297])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_userptr_blits@forbidden-operations.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-rkl:          [SKIP][345] ([i915#14544] / [i915#3297]) -> [SKIP][346] ([i915#3297])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gem_userptr_blits@readonly-unsync.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gen9_exec_parse@unaligned-access:
    - shard-rkl:          [SKIP][347] ([i915#2527]) -> [SKIP][348] ([i915#14544] / [i915#2527]) +1 other test skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@gen9_exec_parse@unaligned-access.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@gen9_exec_parse@unaligned-access.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-rkl:          [SKIP][349] ([i915#14544] / [i915#2527]) -> [SKIP][350] ([i915#2527]) +1 other test skip
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@gen9_exec_parse@valid-registers.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_pm_sseu@full-enable:
    - shard-rkl:          [SKIP][351] ([i915#14544] / [i915#4387]) -> [SKIP][352] ([i915#4387])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@i915_pm_sseu@full-enable.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@i915_pm_sseu@full-enable.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          [SKIP][353] ([i915#1769] / [i915#3555]) -> [SKIP][354] ([i915#14544] / [i915#1769] / [i915#3555])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][355] ([i915#14544] / [i915#5286]) -> [SKIP][356] ([i915#5286]) +3 other tests skip
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-rkl:          [SKIP][357] ([i915#5286]) -> [SKIP][358] ([i915#14544] / [i915#5286]) +4 other tests skip
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-dg1:          [SKIP][359] ([i915#3638]) -> [SKIP][360] ([i915#3638] / [i915#4423])
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-12/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-18/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][361] ([i915#14544] / [i915#3638]) -> [SKIP][362] ([i915#3638])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg1:          [SKIP][363] ([i915#4538]) -> [SKIP][364] ([i915#4423] / [i915#4538])
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-12/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][365] ([i915#12313] / [i915#14544]) -> [SKIP][366] ([i915#12313])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][367] ([i915#14544] / [i915#6095]) -> [SKIP][368] ([i915#6095]) +10 other tests skip
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][369] ([i915#12805] / [i915#14544]) -> [SKIP][370] ([i915#12805])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-rkl:          [SKIP][371] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][372] ([i915#14098] / [i915#6095]) +14 other tests skip
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          [INCOMPLETE][373] ([i915#14694] / [i915#15582]) -> [INCOMPLETE][374] ([i915#15582]) +1 other test incomplete
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-glk3/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk5/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
    - shard-rkl:          [SKIP][375] ([i915#14098] / [i915#6095]) -> [SKIP][376] ([i915#14098] / [i915#14544] / [i915#6095]) +13 other tests skip
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][377] ([i915#6095]) -> [SKIP][378] ([i915#14544] / [i915#6095]) +6 other tests skip
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-rkl:          [SKIP][379] ([i915#11151] / [i915#7828]) -> [SKIP][380] ([i915#11151] / [i915#14544] / [i915#7828]) +7 other tests skip
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-3/igt@kms_chamelium_frames@hdmi-crc-fast.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-rkl:          [SKIP][381] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][382] ([i915#11151] / [i915#7828]) +2 other tests skip
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_content_protection@content-type-change:
    - shard-rkl:          [SKIP][383] ([i915#15865]) -> [SKIP][384] ([i915#14544] / [i915#15865])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_content_protection@content-type-change.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-rkl:          [SKIP][385] ([i915#15330] / [i915#3116]) -> [SKIP][386] ([i915#14544] / [i915#15330] / [i915#3116])
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_content_protection@dp-mst-type-1.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@suspend-resume:
    - shard-dg2:          [SKIP][387] ([i915#15865]) -> [FAIL][388] ([i915#7173])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-4/igt@kms_content_protection@suspend-resume.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@kms_content_protection@suspend-resume.html
    - shard-rkl:          [SKIP][389] ([i915#14544] / [i915#15865]) -> [SKIP][390] ([i915#15865]) +1 other test skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_content_protection@suspend-resume.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_content_protection@suspend-resume.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2:          [SKIP][391] ([i915#13049]) -> [SKIP][392] ([i915#13049] / [i915#3359])
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          [SKIP][393] ([i915#13049]) -> [SKIP][394] ([i915#13049] / [i915#14544])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][395] ([i915#4103]) -> [SKIP][396] ([i915#14544] / [i915#4103]) +1 other test skip
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-rkl:          [SKIP][397] ([i915#14544] / [i915#4103]) -> [SKIP][398] ([i915#4103])
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg1:          [SKIP][399] ([i915#4103] / [i915#4213]) -> [SKIP][400] ([i915#4103] / [i915#4213] / [i915#4423])
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-15/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-19/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-rkl:          [SKIP][401] ([i915#13749] / [i915#14544]) -> [SKIP][402] ([i915#13749])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_dp_link_training@non-uhbr-mst.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          [SKIP][403] ([i915#13748]) -> [SKIP][404] ([i915#13748] / [i915#14544])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_dp_link_training@uhbr-sst.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          [SKIP][405] ([i915#13707] / [i915#14544]) -> [SKIP][406] ([i915#13707])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_feature_discovery@chamelium:
    - shard-rkl:          [SKIP][407] ([i915#14544] / [i915#4854]) -> [SKIP][408] ([i915#4854])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_feature_discovery@chamelium.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          [SKIP][409] ([i915#658]) -> [SKIP][410] ([i915#14544] / [i915#658])
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_feature_discovery@psr1.html
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_feature_discovery@psr2:
    - shard-rkl:          [SKIP][411] ([i915#14544] / [i915#658]) -> [SKIP][412] ([i915#658])
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_feature_discovery@psr2.html
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-rkl:          [SKIP][413] ([i915#14544] / [i915#9934]) -> [SKIP][414] ([i915#9934]) +3 other tests skip
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_flip@2x-blocking-wf_vblank.html
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          [SKIP][415] ([i915#9934]) -> [SKIP][416] ([i915#14544] / [i915#9934]) +2 other tests skip
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_flip@2x-plain-flip.html
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][417] ([i915#12745] / [i915#4839]) -> [INCOMPLETE][418] ([i915#12745] / [i915#4839] / [i915#6113])
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-glk9/igt@kms_flip@flip-vs-suspend.html
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk3/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
    - shard-glk:          [INCOMPLETE][419] ([i915#12745]) -> [INCOMPLETE][420] ([i915#12745] / [i915#6113])
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-glk9/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-glk3/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][421] ([i915#14544] / [i915#15643]) -> [SKIP][422] ([i915#15643])
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][423] ([i915#15643]) -> [SKIP][424] ([i915#14544] / [i915#15643]) +3 other tests skip
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][425] ([i915#15102]) -> [SKIP][426] ([i915#14544] / [i915#15102])
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][427] ([i915#14544] / [i915#15102]) -> [SKIP][428] ([i915#15102])
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][429] ([i915#1825]) -> [SKIP][430] ([i915#14544] / [i915#1825]) +14 other tests skip
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
    - shard-dg1:          [SKIP][431] ([i915#4423]) -> [SKIP][432]
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][433] ([i915#14544] / [i915#1825]) -> [SKIP][434] ([i915#1825]) +22 other tests skip
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
    - shard-dg1:          [SKIP][435] ([i915#8708]) -> [SKIP][436] ([i915#4423] / [i915#8708])
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - shard-rkl:          [SKIP][437] ([i915#15102] / [i915#3023]) -> [SKIP][438] ([i915#14544] / [i915#15102] / [i915#3023]) +11 other tests skip
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-rkl:          [SKIP][439] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][440] ([i915#15102] / [i915#3023]) +4 other tests skip
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg2:          [SKIP][441] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][442] ([i915#15102] / [i915#3458]) +2 other tests skip
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-dg1:          [SKIP][443] ([i915#15102] / [i915#3458]) -> [SKIP][444] ([i915#15102] / [i915#3458] / [i915#4423])
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-mtlp:         [SKIP][445] ([i915#1187] / [i915#12713]) -> [SKIP][446] ([i915#12713])
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-mtlp-1/igt@kms_hdr@brightness-with-hdr.html
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-mtlp-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-rkl:          [SKIP][447] ([i915#13688] / [i915#14544]) -> [SKIP][448] ([i915#13688])
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_joiner@basic-max-non-joiner.html
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-rkl:          [SKIP][449] ([i915#14544] / [i915#15709]) -> [SKIP][450] ([i915#15709])
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-modifier:
    - shard-rkl:          [SKIP][451] ([i915#15709]) -> [SKIP][452] ([i915#14544] / [i915#15709]) +1 other test skip
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-modifier.html
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-modifier.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-rkl:          [SKIP][453] ([i915#13958]) -> [SKIP][454] ([i915#13958] / [i915#14544])
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_plane_multiple@2x-tiling-yf.html
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
    - shard-rkl:          [SKIP][455] ([i915#14544] / [i915#15329] / [i915#3555]) -> [SKIP][456] ([i915#15329] / [i915#3555])
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b:
    - shard-rkl:          [SKIP][457] ([i915#14544] / [i915#15329]) -> [SKIP][458] ([i915#15329]) +2 other tests skip
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-c:
    - shard-rkl:          [SKIP][459] ([i915#15329]) -> [SKIP][460] ([i915#14544] / [i915#15329]) +7 other tests skip
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-c.html
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-c.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-rkl:          [SKIP][461] ([i915#14544] / [i915#15739]) -> [SKIP][462] ([i915#15739])
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_pm_dc@dc9-dpms.html
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg1:          [SKIP][463] ([i915#9340]) -> [SKIP][464] ([i915#3828])
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-18/igt@kms_pm_lpsp@kms-lpsp.html
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-14/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@package-g7:
    - shard-rkl:          [SKIP][465] ([i915#15403]) -> [SKIP][466] ([i915#14544] / [i915#15403])
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-4/igt@kms_pm_rpm@package-g7.html
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-dg1:          [SKIP][467] ([i915#11520]) -> [SKIP][468] ([i915#11520] / [i915#4423])
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-12/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-18/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][469] ([i915#11520] / [i915#14544]) -> [SKIP][470] ([i915#11520]) +2 other tests skip
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][471] ([i915#11520]) -> [SKIP][472] ([i915#11520] / [i915#14544]) +5 other tests skip
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          [SKIP][473] ([i915#14544] / [i915#9683]) -> [SKIP][474] ([i915#9683])
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_psr2_su@page_flip-nv12.html
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-rkl:          [SKIP][475] ([i915#1072] / [i915#9732]) -> [SKIP][476] ([i915#1072] / [i915#14544] / [i915#9732]) +10 other tests skip
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr-dpms:
    - shard-rkl:          [SKIP][477] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][478] ([i915#1072] / [i915#9732]) +8 other tests skip
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_psr@fbc-psr-dpms.html
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_psr@fbc-psr-dpms.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          [SKIP][479] ([i915#12755] / [i915#15867]) -> [SKIP][480] ([i915#15867])
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg2-4/igt@kms_rotation_crc@primary-rotation-270.html
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg2-10/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-rkl:          [SKIP][481] ([i915#14544] / [i915#5289]) -> [SKIP][482] ([i915#5289])
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-rkl:          [SKIP][483] ([i915#5289]) -> [SKIP][484] ([i915#14544] / [i915#5289])
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          [SKIP][485] ([i915#3555]) -> [SKIP][486] ([i915#14544] / [i915#3555])
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_scaling_modes@scaling-mode-none.html
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-rkl:          [SKIP][487] ([i915#14544] / [i915#3555]) -> [SKIP][488] ([i915#3555]) +1 other test skip
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc.html
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg1:          [SKIP][489] ([i915#8623]) -> [SKIP][490] ([i915#4423] / [i915#8623])
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-dg1-15/igt@kms_tiled_display@basic-test-pattern.html
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-dg1-13/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@flip-basic:
    - shard-rkl:          [SKIP][491] ([i915#15243] / [i915#3555]) -> [SKIP][492] ([i915#14544] / [i915#15243] / [i915#3555]) +1 other test skip
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@kms_vrr@flip-basic.html
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@kms_vrr@flip-basic.html

  * igt@perf@mi-rpc:
    - shard-rkl:          [SKIP][493] ([i915#14544] / [i915#2434]) -> [SKIP][494] ([i915#2434])
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@perf@mi-rpc.html
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-8/igt@perf@mi-rpc.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-rkl:          [SKIP][495] ([i915#14544]) -> [SKIP][496] +8 other tests skip
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-6/igt@perf_pmu@event-wait@rcs0.html
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-3/igt@perf_pmu@event-wait@rcs0.html

  * igt@prime_vgem@coherency-gtt:
    - shard-rkl:          [SKIP][497] ([i915#3708]) -> [SKIP][498] ([i915#14544] / [i915#3708])
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18295/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/shard-rkl-6/igt@prime_vgem@coherency-gtt.html

  
  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
  [i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
  [i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13030
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13363]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13363
  [i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
  [i915#13562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13562
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13705]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13705
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
  [i915#14694]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14694
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15106]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15106
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15403
  [i915#15420]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15420
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15481]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15481
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15638
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15672
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15718]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15718
  [i915#15722]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15722
  [i915#15739]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15739
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * Linux: CI_DRM_18295 -> Patchwork_164567v1

  CI-20190529: 20190529
  CI_DRM_18295: 08037efa91c349ee17b62ddd1908a846d7abd917 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8850: 8850
  Patchwork_164567v1: 08037efa91c349ee17b62ddd1908a846d7abd917 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v1/index.html

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