From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DA87C77B75 for ; Fri, 12 May 2023 22:29:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D071B10E6DA; Fri, 12 May 2023 22:29:27 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id DB77210E6DA for ; Fri, 12 May 2023 22:29:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683930565; x=1715466565; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=nJG2BUADNt7OxP9IZE6oUmMKc4s15KhPo4mtdf3Dmcg=; b=FYOwC+49HzvGHT5CGr7YrbHwwtn/NC6uP7BnlxOw3P9G0gohYYi1OBiF I3tI3zVvgflqkxOXlEbpuZMKYSgAHCZRCWkOiZPwe1rkWejM36N6VvCKw TOCmQve9rS/wDN+mJ0qoLUr2YUBwoMCoER6/xq3Scus20plpZgtp2/ZmJ 46RukNZ09c0gZXsct2/flOf+dpUXSLq58yc211MlqVC+TFjEAUxZ8RvFo 6w0U9vvVHMSkL1WTfqMr52RILsrOEJ9E66NfyipV1n1Dvu4yfm1EoFfBQ V8sO5a4+gnHw3Yz2xmpesuvZ/WDi8WDc3Fp42A5sXe4wcPytg+A2sipix g==; X-IronPort-AV: E=McAfee;i="6600,9927,10708"; a="340222223" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="340222223" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2023 15:29:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10708"; a="946776326" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="946776326" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.239.47]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2023 15:29:23 -0700 Date: Fri, 12 May 2023 15:29:03 -0700 Message-ID: <87ilcxdw0g.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20230506005816.1891043-5-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> <20230506005816.1891043-5-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: > Hi Umesh/Tvrtko, > From: Tvrtko Ursulin > > We do not want to have timers per tile and waste CPU cycles and energy via > multiple wake-up sources, for a relatively un-important task of PMU > sampling, so keeping a single timer works well. But we also do not want > the first GT which goes idle to turn off the timer. > > Add some reference counting, via a mask of unparked GTs, to solve this. > > Signed-off-by: Tvrtko Ursulin > Signed-off-by: Umesh Nerlige Ramappa > --- > drivers/gpu/drm/i915/i915_pmu.c | 12 ++++++++++-- > drivers/gpu/drm/i915/i915_pmu.h | 4 ++++ > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 2b63ee31e1b3..669a42e44082 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt) > * Signal sampling timer to stop if only engine events are enabled and > * GPU went idle. > */ > - pmu->timer_enabled = pmu_needs_timer(pmu, false); > + pmu->unparked &= ~BIT(gt->info.id); > + if (pmu->unparked == 0) > + pmu->timer_enabled = pmu_needs_timer(pmu, false); > > spin_unlock_irq(&pmu->lock); > } > @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt) > /* > * Re-enable sampling timer when GPU goes active. > */ > - __i915_pmu_maybe_start_timer(pmu); > + if (pmu->unparked == 0) > + __i915_pmu_maybe_start_timer(pmu); > + > + pmu->unparked |= BIT(gt->info.id); > > spin_unlock_irq(&pmu->lock); > } > @@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) > */ > > for_each_gt(gt, i915, i) { > + if (!(pmu->unparked & BIT(i))) > + continue; > + This is not correct. In this series we are at least sampling frequencies (calling frequency_sample) even when GT is parked. So these 3 lines should be deleted. engines_sample will get called and will return without doing anything if engine events are disabled. Thanks. -- Ashutosh > engines_sample(gt, period_ns); > > if (i == 0) /* FIXME */ > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h > index a686fd7ccedf..3a811266ac6a 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.h > +++ b/drivers/gpu/drm/i915/i915_pmu.h > @@ -76,6 +76,10 @@ struct i915_pmu { > * @lock: Lock protecting enable mask and ref count handling. > */ > spinlock_t lock; > + /** > + * @unparked: GT unparked mask. > + */ > + unsigned int unparked; > /** > * @timer: Timer for internal i915 PMU sampling. > */ > -- > 2.36.1 >