* [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-09-29 21:01 [PATCH] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage James Ausmus
@ 2017-10-04 20:09 ` James Ausmus
2017-10-04 20:28 ` Rodrigo Vivi
0 siblings, 1 reply; 9+ messages in thread
From: James Ausmus @ 2017-10-04 20:09 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
the meaning of the (3 << 26) value varies per platform, but it's always the
maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
it means 3200us.
v2:
-Split in to two patches (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39ad9327e2a0..0324e0ca7597 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5239,7 +5239,7 @@ enum {
#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
+#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 90e756c76f10..5b4c9484575b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1044,7 +1044,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_DONE |
(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_1600us |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-10-04 20:09 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
@ 2017-10-04 20:28 ` Rodrigo Vivi
0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2017-10-04 20:28 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
On Wed, Oct 04, 2017 at 08:09:21PM +0000, James Ausmus wrote:
> Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
> the meaning of the (3 << 26) value varies per platform, but it's always the
> maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
> it means 3200us.
Yeap...
>
> v2:
> -Split in to two patches (Rodrigo)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 39ad9327e2a0..0324e0ca7597 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5239,7 +5239,7 @@ enum {
> #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
> #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
> #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
> -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
> +#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
makes sense for me...
I was going to complain about the tab+spaces but I notice the whole block
there is already like this so nevermind ;)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
> #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 90e756c76f10..5b4c9484575b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1044,7 +1044,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> DP_AUX_CH_CTL_DONE |
> (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
> DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - DP_AUX_CH_CTL_TIME_OUT_1600us |
> + DP_AUX_CH_CTL_TIME_OUT_MAX |
> DP_AUX_CH_CTL_RECEIVE_ERROR |
> (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> --
> 2.14.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
@ 2017-10-12 21:30 James Ausmus
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: James Ausmus @ 2017-10-12 21:30 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
the meaning of the (3 << 26) value varies per platform, but it's always the
maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
it means 3200us.
v2:
-Split in to two patches (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2d0a83c09b6..5f99d4d6291b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5242,7 +5242,7 @@ enum {
#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
+#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 753404280a19..3f0d37fa833f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1032,7 +1032,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_DONE |
(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_1600us |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-12 21:30 [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
@ 2017-10-12 21:30 ` James Ausmus
2017-10-12 21:52 ` Rodrigo Vivi
2017-10-12 21:52 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming Rodrigo Vivi
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: James Ausmus @ 2017-10-12 21:30 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
Set BDW to 600us unconditionally.
v2:
-Split in to two patches (Rodrigo)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3f0d37fa833f..4b65cf137f79 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1007,7 +1007,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
else
precharge = 5;
- if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
+ if (IS_BROADWELL(dev_priv))
timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
else
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-10-12 21:30 [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
@ 2017-10-12 21:52 ` Rodrigo Vivi
2017-10-13 8:44 ` Jani Nikula
2017-10-12 22:01 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] " Patchwork
2017-10-13 4:37 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2017-10-12 21:52 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
On Thu, Oct 12, 2017 at 09:30:36PM +0000, James Ausmus wrote:
> Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
> the meaning of the (3 << 26) value varies per platform, but it's always the
> maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
> it means 3200us.
>
> v2:
> -Split in to two patches (Rodrigo)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
you could've added the rv-b already: ;)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d2d0a83c09b6..5f99d4d6291b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5242,7 +5242,7 @@ enum {
> #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
> #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
> #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
> -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
> +#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
> #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
> #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 753404280a19..3f0d37fa833f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1032,7 +1032,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> DP_AUX_CH_CTL_DONE |
> (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
> DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - DP_AUX_CH_CTL_TIME_OUT_1600us |
> + DP_AUX_CH_CTL_TIME_OUT_MAX |
> DP_AUX_CH_CTL_RECEIVE_ERROR |
> (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> --
> 2.14.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
@ 2017-10-12 21:52 ` Rodrigo Vivi
0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2017-10-12 21:52 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
On Thu, Oct 12, 2017 at 09:30:37PM +0000, James Ausmus wrote:
> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
> Set BDW to 600us unconditionally.
>
> v2:
> -Split in to two patches (Rodrigo)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
same
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3f0d37fa833f..4b65cf137f79 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1007,7 +1007,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> else
> precharge = 5;
>
> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
> + if (IS_BROADWELL(dev_priv))
> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> else
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> --
> 2.14.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-10-12 21:30 [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
2017-10-12 21:52 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming Rodrigo Vivi
@ 2017-10-12 22:01 ` Patchwork
2017-10-13 4:37 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-12 22:01 UTC (permalink / raw)
To: Ausmus, James; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
URL : https://patchwork.freedesktop.org/series/31856/
State : success
== Summary ==
Series 31856v1 series starting with [v2,1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
https://patchwork.freedesktop.org/api/1.0/series/31856/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
fail -> PASS (fi-kbl-7500u) fdo#102514
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (fi-byt-j1900) fdo#101705
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:461s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:470s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:396s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:580s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:287s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:527s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:528s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:539s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:528s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:562s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:438s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:275s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:607s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:438s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:463s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:502s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:481s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:505s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:487s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:597s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:476s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:666s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:535s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:512s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:480s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:589s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:434s
fi-pnv-d510 failed to connect after reboot
490bd134d63554815d2ea6ff56e6d32fd50ff472 drm-tip: 2017y-10m-12d-20h-08m-10s UTC integration manifest
6337cc32a524 drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
84096eab1ae4 drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6016/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-10-12 21:30 [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
` (2 preceding siblings ...)
2017-10-12 22:01 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] " Patchwork
@ 2017-10-13 4:37 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-13 4:37 UTC (permalink / raw)
To: Ausmus, James; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
URL : https://patchwork.freedesktop.org/series/31856/
State : success
== Summary ==
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2552 pass:1439 dwarn:0 dfail:0 fail:10 skip:1103 time:9610s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6016/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-10-12 21:52 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming Rodrigo Vivi
@ 2017-10-13 8:44 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2017-10-13 8:44 UTC (permalink / raw)
To: Rodrigo Vivi, James Ausmus; +Cc: intel-gfx
On Thu, 12 Oct 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Thu, Oct 12, 2017 at 09:30:36PM +0000, James Ausmus wrote:
>> Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
>> the meaning of the (3 << 26) value varies per platform, but it's always the
>> maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
>> it means 3200us.
>>
>> v2:
>> -Split in to two patches (Rodrigo)
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: James Ausmus <james.ausmus@intel.com>
>
> you could've added the rv-b already: ;)
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Pushed both as the CI results arrived in my time zone, thanks for the
patches and review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> drivers/gpu/drm/i915/intel_dp.c | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d2d0a83c09b6..5f99d4d6291b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5242,7 +5242,7 @@ enum {
>> #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
>> #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
>> #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
>> -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
>> +#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
>> #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
>> #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
>> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 753404280a19..3f0d37fa833f 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1032,7 +1032,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
>> DP_AUX_CH_CTL_DONE |
>> (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
>> DP_AUX_CH_CTL_TIME_OUT_ERROR |
>> - DP_AUX_CH_CTL_TIME_OUT_1600us |
>> + DP_AUX_CH_CTL_TIME_OUT_MAX |
>> DP_AUX_CH_CTL_RECEIVE_ERROR |
>> (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
>> DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
>> --
>> 2.14.1
>>
--
Jani Nikula, Intel Open Source Technology Center
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Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-12 21:30 [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
2017-10-12 21:52 ` Rodrigo Vivi
2017-10-12 21:52 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming Rodrigo Vivi
2017-10-13 8:44 ` Jani Nikula
2017-10-12 22:01 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] " Patchwork
2017-10-13 4:37 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-09-29 21:01 [PATCH] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage James Ausmus
2017-10-04 20:09 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2017-10-04 20:28 ` Rodrigo Vivi
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