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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/8] drm/i915: Disable irqs across GPU reset
Date: Mon, 03 Oct 2016 16:09:24 +0300	[thread overview]
Message-ID: <87int94m0r.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20161003125246.17686-4-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Whilst we reset the GPU, we want to prevent execlists from submitting
> new work (which it does via an interrupt handler). To achieve this we
> disable the irq (and drain the irq tasklet) around the reset. When we
> enable it again afters, the interrupt queue should be empty and we can
> reinitialise from a known state without fear of the tasklet running
> concurrently.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>

Restamping

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_gem.c |  2 --
>  2 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 31b2b6300d8d..7ce498898217 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1728,6 +1728,21 @@ int i915_resume_switcheroo(struct drm_device *dev)
>  	return i915_drm_resume(dev);
>  }
>  
> +static void disable_engines_irq(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_engine_cs *engine;
> +
> +	/* Ensure irq handler finishes, and not run again. */
> +	disable_irq(dev_priv->drm.irq);
> +	for_each_engine(engine, dev_priv)
> +		tasklet_kill(&engine->irq_tasklet);
> +}
> +
> +static void enable_engines_irq(struct drm_i915_private *dev_priv)
> +{
> +	enable_irq(dev_priv->drm.irq);
> +}
> +
>  /**
>   * i915_reset - reset chip after a hang
>   * @dev: drm device to reset
> @@ -1761,7 +1776,11 @@ void i915_reset(struct drm_i915_private *dev_priv)
>  	error->reset_count++;
>  
>  	pr_notice("drm/i915: Resetting chip after gpu hang\n");
> +
> +	disable_engines_irq(dev_priv);
>  	ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
> +	enable_engines_irq(dev_priv);
> +
>  	if (ret) {
>  		if (ret != -ENODEV)
>  			DRM_ERROR("Failed to reset chip: %i\n", ret);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1418c1c522cb..0cae8acdf906 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2581,8 +2581,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine)
>  	struct i915_gem_context *incomplete_ctx;
>  	bool ring_hung;
>  
> -	/* Ensure irq handler finishes, and not run again. */
> -	tasklet_kill(&engine->irq_tasklet);
>  	if (engine->irq_seqno_barrier)
>  		engine->irq_seqno_barrier(engine);
>  
> -- 
> 2.9.3
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  reply	other threads:[~2016-10-03 13:09 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-03 12:52 [PATCH 1/8] drm/i915: Share the computation of ring size for RING_CTL register Chris Wilson
2016-10-03 12:52 ` [PATCH 2/8] drm/i915/execlists: Reinitialise context image after GPU hang Chris Wilson
2016-10-03 12:52 ` [PATCH 3/8] drm/i915/execlists: Move clearing submission count from reset to init Chris Wilson
2016-10-03 13:07   ` Mika Kuoppala
2016-10-03 12:52 ` [PATCH 4/8] drm/i915: Disable irqs across GPU reset Chris Wilson
2016-10-03 13:09   ` Mika Kuoppala [this message]
2016-10-03 12:52 ` [PATCH 5/8] drm/i915: Double check hangcheck.seqno after reset Chris Wilson
2016-10-03 13:14   ` Mika Kuoppala
2016-10-03 14:01     ` Chris Wilson
2016-10-03 12:52 ` [PATCH 6/8] drm/i915: Show bounds of active request in the ring on GPU hang Chris Wilson
2016-10-04 11:56   ` Mika Kuoppala
2016-10-03 12:52 ` [PATCH 7/8] drm/i915: Show RING registers through debugfs Chris Wilson
2016-10-04 12:35   ` Mika Kuoppala
2016-10-04 13:11     ` Chris Wilson
2016-10-03 12:52 ` [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info Chris Wilson
2016-10-04 12:41   ` Mika Kuoppala
2016-10-04 13:07     ` Chris Wilson
2016-10-04 13:22   ` Mika Kuoppala
2016-10-03 13:00 ` [PATCH 1/8] drm/i915: Share the computation of ring size for RING_CTL register Chris Wilson
2016-10-04 12:51   ` Mika Kuoppala
2016-10-03 13:01 ` Mika Kuoppala
2016-10-03 14:49 ` ✗ Fi.CI.BAT: warning for series starting with [1/8] " Patchwork

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