From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Cc: Deepak M <m.deepak@intel.com>
Subject: Re: [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it
Date: Wed, 16 Mar 2016 10:45:52 +0200 [thread overview]
Message-ID: <87io0mx133.fsf@intel.com> (raw)
In-Reply-To: <1458052809-23426-11-git-send-email-ville.syrjala@linux.intel.com>
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On VLV at least, the BIOS may leave the DSI PLL enabled in some wonky
> state where it just refuses to lock. Simply disabling the PLL before
> reconfiguring it is not enough to fix it, but power gating the PLL
> prior to reconfiguring does work.
>
> This happens on BYT FFRD8 when booting with HDMI connected so the DSI
> display will not be lit up by the BIOS.
>
> Also we can remove the code for BXT that disables the PLL before
> enabling it again.
>
> v2: s/vlv/intel/ since BXT made thing generic
> v3: Remove the BXT disable PLL before enable trick
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 8 --------
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 4023b6bffa47..787411e1c36f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -482,7 +482,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> + /*
> + * The BIOS may leave the PLL in a wonky state where it doesn't
> + * lock. It needs to be fully powered down to fix it.
> + */
> + intel_disable_dsi_pll(encoder);
> intel_enable_dsi_pll(encoder);
> +
> intel_dsi_prepare(encoder);
>
> /* Panel Enable over CRC PMIC */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 916cc92c1400..978cc2668a3d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -474,14 +474,6 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> - val = I915_READ(BXT_DSI_PLL_ENABLE);
> -
> - if (val & BXT_DSI_PLL_DO_ENABLE) {
> - WARN(1, "DSI PLL already enabled. Disabling it.\n");
> - val &= ~BXT_DSI_PLL_DO_ENABLE;
> - I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> - }
> -
> /* Configure PLL vales */
> if (!bxt_configure_dsi_pll(encoder)) {
> DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2016-03-16 8:45 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
2016-03-15 14:39 ` [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions ville.syrjala
2016-03-16 9:02 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar ville.syrjala
2016-03-30 13:31 ` Jani Nikula
2016-04-01 19:59 ` Ville Syrjälä
2016-03-15 14:39 ` [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv ville.syrjala
2016-03-16 9:27 ` Jani Nikula
2016-03-16 13:07 ` Ville Syrjälä
2016-03-15 14:39 ` [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll() ville.syrjala
2016-03-16 9:03 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll() ville.syrjala
2016-03-16 9:04 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll() ville.syrjala
2016-03-16 9:05 ` Jani Nikula
2016-04-01 19:58 ` Ville Syrjälä
2016-03-15 14:40 ` [PATCH 07/16] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV ville.syrjala
2016-03-15 14:40 ` [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled ville.syrjala
2016-03-16 9:06 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16 ville.syrjala
2016-03-16 8:42 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it ville.syrjala
2016-03-16 8:45 ` Jani Nikula [this message]
2016-03-15 14:40 ` [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config() ville.syrjala
2016-03-16 8:56 ` Jani Nikula
2016-03-16 12:59 ` Ville Syrjälä
2016-03-15 14:40 ` [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout ville.syrjala
2016-03-16 8:58 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll() ville.syrjala
2016-03-16 8:59 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex ville.syrjala
2016-03-16 9:00 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 15/16] drm/i915: Hook up pfit for DSI ville.syrjala
2016-03-30 13:35 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms ville.syrjala
2016-03-30 13:36 ` Jani Nikula
2016-03-15 15:27 ` ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly Patchwork
2016-04-01 19:12 ` Ville Syrjälä
2016-04-01 19:39 ` Chris Wilson
2016-04-01 19:47 ` Ville Syrjälä
2016-04-01 19:53 ` Chris Wilson
2016-04-12 18:39 ` [PATCH 00/16] " Ville Syrjälä
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