From: Francisco Jerez <currojerez@riseup.net>
To: Jordan Justen <jordan.l.justen@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Kenneth Graunke <kenneth@whitecape.org>
Subject: Re: [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist
Date: Tue, 08 Mar 2016 14:06:04 -0800 [thread overview]
Message-ID: <87io0wfwvn.fsf@riseup.net> (raw)
In-Reply-To: <1457335830-30923-2-git-send-email-jordan.l.justen@intel.com>
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Jordan Justen <jordan.l.justen@intel.com> writes:
> This is needed for the Mesa Vulkan driver on Haswell.
>
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Kristian Høgsberg <krh@bitplanet.net>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 814d894..86d7cda 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -444,6 +444,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> REG64(CL_PRIMITIVES_COUNT),
> REG64(PS_INVOCATION_COUNT),
> REG64(PS_DEPTH_COUNT),
> + REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
> REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
> REG64(MI_PREDICATE_SRC0),
> REG64(MI_PREDICATE_SRC1),
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2016-03-08 22:06 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
2016-03-07 7:30 ` [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist Jordan Justen
2016-03-08 22:06 ` Francisco Jerez [this message]
2016-03-07 7:30 ` [PATCH 2/5] drm/i915: Use an array of register tables in command parser Jordan Justen
2016-03-16 23:33 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 3/5] drm/i915: Move Haswell registers to separate whitelist table Jordan Justen
2016-03-08 22:05 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist Jordan Justen
2016-03-08 22:06 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers Jordan Justen
2016-03-08 22:07 ` Francisco Jerez
2016-03-21 9:03 ` Daniel Vetter
2016-03-07 12:27 ` ✗ Fi.CI.BAT: failure for Haswell Command Parser updates for Vulkan Patchwork
2016-03-21 8:53 ` Daniel Vetter
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