From: Francisco Jerez <currojerez@riseup.net>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations.
Date: Wed, 02 Oct 2013 15:31:40 -0700 [thread overview]
Message-ID: <87ioxfuwxf.fsf@riseup.net> (raw)
In-Reply-To: <CAKMK7uErnpuPgvw3smAtbpH6TvH_K8VjqS59c0rtQ+yW1yxwFw@mail.gmail.com>
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Daniel Vetter <daniel@ffwll.ch> writes:
> On Thu, Oct 3, 2013 at 12:03 AM, Francisco Jerez <currojerez@riseup.net> wrote:
>> + case I915_PARAM_HAS_ATOMICS:
>> + value = 1;
>> + break;
>
> Generally when we do kernel fixes for gpu hangs like that we don't add
> parameters (would drown in them otherwise) but simply queue it up to
> -fixes and slap a cc: stable on it. Gpu hang fixes are critical enough
> imo for that treatment, even when it's for brand new userspace code.
>
> Any specific reason why we shouldn't follow this approach here? I'd
> make the patch simpler and we could dump a bit of userspace code, too.
> -Daniel
Not really, I'm fine either way. I'll send a revised version of this
patch without the param change.
Thanks.
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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next prev parent reply other threads:[~2013-10-02 22:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-02 22:03 [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations Francisco Jerez
2013-10-02 22:16 ` Ben Widawsky
2013-10-02 22:20 ` Daniel Vetter
2013-10-02 22:31 ` Francisco Jerez [this message]
2013-10-02 22:31 ` Ben Widawsky
2013-10-02 22:53 ` Francisco Jerez
2013-10-03 7:35 ` Daniel Vetter
2013-10-03 1:36 ` Eric Anholt
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