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d="scan'208";a="32518767" Received: from unknown (HELO localhost) ([10.245.246.99]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 06:16:20 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Subject: Re: [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies In-Reply-To: <20240516135622.3498-12-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20240516135622.3498-1-ville.syrjala@linux.intel.com> <20240516135622.3498-12-ville.syrjala@linux.intel.com> Date: Mon, 20 May 2024 16:16:17 +0300 Message-ID: <87jzjosjxa.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Add some notes indicatign which plane registers/bits are *indicating > valid for which platforms. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Acked-by: Jani Nikula because I'm not going to chase through all the specs for these. ;) > --- > .../gpu/drm/i915/display/i9xx_plane_regs.h | 22 +++++++++---------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu= /drm/i915/display/i9xx_plane_regs.h > index 929b26faf31e..d74a74d1f29a 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > @@ -37,53 +37,53 @@ > #define DISP_LINE_DOUBLE REG_BIT(20) > #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) > #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ > -#define DISP_ROTATE_180 REG_BIT(15) > +#define DISP_ROTATE_180 REG_BIT(15) /* i965+ */ > #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ > -#define DISP_TILED REG_BIT(10) > +#define DISP_TILED REG_BIT(10) /* i965+ */ > #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ > #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ >=20=20 > -#define _DSPAADDR 0x70184 > +#define _DSPAADDR 0x70184 /* pre-i965 */ > #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) >=20=20 > -#define _DSPALINOFF 0x70184 > +#define _DSPALINOFF 0x70184 /* i965+ */ > #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) >=20=20 > #define _DSPASTRIDE 0x70188 > #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) >=20=20 > -#define _DSPAPOS 0x7018C /* reserved */ > +#define _DSPAPOS 0x7018C /* pre-g4x */ > #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) > #define DISP_POS_Y_MASK REG_GENMASK(31, 16) > #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) > #define DISP_POS_X_MASK REG_GENMASK(15, 0) > #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) >=20=20 > -#define _DSPASIZE 0x70190 > +#define _DSPASIZE 0x70190 /* pre-g4x */ > #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) > #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) > #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) > #define DISP_WIDTH_MASK REG_GENMASK(15, 0) > #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) >=20=20 > -#define _DSPASURF 0x7019C /* 965+ only */ > +#define _DSPASURF 0x7019C /* i965+ */ > #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) > #define DISP_ADDR_MASK REG_GENMASK(31, 12) >=20=20 > -#define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define _DSPATILEOFF 0x701A4 /* i965+ */ > #define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) > #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) > #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) > #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) >=20=20 > -#define _DSPAOFFSET 0x701A4 /* HSW */ > +#define _DSPAOFFSET 0x701A4 /* hsw+ */ > #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) >=20=20 > -#define _DSPASURFLIVE 0x701AC > +#define _DSPASURFLIVE 0x701AC /* g4x+ */ > #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) >=20=20 > -#define _DSPAGAMC 0x701E0 > +#define _DSPAGAMC 0x701E0 /* pre-g4x */ > #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 = - (i)) * 4) /* plane C only, 6 x u0.8 */ >=20=20 > /* CHV pipe B primary plane */ --=20 Jani Nikula, Intel