From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1AC4C678D5 for ; Wed, 8 Mar 2023 05:36:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DF51410E309; Wed, 8 Mar 2023 05:36:08 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 830FA10E2AB; Wed, 8 Mar 2023 05:36:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678253766; x=1709789766; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=Y1rsL1rkgiQXdtTZqMp0wlABoY/a8HncB2KN6HKdbuc=; b=hLy7NDP/p2ehjl8z1+b0dTrc8zezHEuV0BiIRF13r2TTAVS29J8mh9Kr aBIu1Hn1PVAEuqahFcmU9AX9i51l6VPFbbl4iAbmrrSjXG1r+XQzF7s9G GzxbjFlOVLoHa1o4rad5T5l24SqBTviO+pm2SUXtJ7dqLeEJNJcSwCc/Z L5ZQqbxEuPiGIs/tyIPkJP627MDyPH2DZzHFugwNUt/h62I2T0cVKehBb 998lSYcRbI4uI72a+lvYEXhzb6Aed8YusEB38lRAwEVFMcclgmBSiAmY6 y22fv58U3mziHbKXmahtNtuBzSpo6YwrJtjE6u8cxaT5kW+eiGBylVIFn A==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="334781937" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="334781937" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:36:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745777129" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="745777129" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.87.208]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:36:05 -0800 Date: Tue, 07 Mar 2023 21:36:05 -0800 Message-ID: <87jzzrn6t6.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Tvrtko Ursulin In-Reply-To: <6abc2ea5-4d60-765b-a830-ee0225c63871@linux.intel.com> References: <20230304012705.70003-1-ashutosh.dixit@intel.com> <20230304012705.70003-2-ashutosh.dixit@intel.com> <6abc2ea5-4d60-765b-a830-ee0225c63871@linux.intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use only freq bits for falling back to requested freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 06 Mar 2023 03:04:40 -0800, Tvrtko Ursulin wrote: > Hi Tvrtko, > On 04/03/2023 01:27, Ashutosh Dixit wrote: > > On newer generations, the GEN12_RPSTAT1 register contains more than freq > > information, e.g. see GEN12_VOLTAGE_MASK. Therefore use only the freq bits > > to decide whether to fall back to requested freq. > > CI is not catching the problem? This is because as we know PMU freq sampling happens only when gt is unparked (actively processing requests) so it is highly unlikely that gt will be in rc6 when it might have to fall back to requested freq (I checked this and it seems it is only at the end of the workload that we see it entering the fallback code path). Deleting the fallback path completely will not make much difference to the output and is an option too. Anyway I have retained it for now. > Could you find an appropriate Fixes: tag please? If it can affects a > platform out of force probe then cc: stable to. Cc stable is anyway not needed because affected platforms (DG1 onwards) are under force probe. Also because the issue does not affect real metrics (as mentioned above) as well as because it is a really a missing patch rather than a broken previous patch I am skipping the Fixes tag. > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/i915_pmu.c | 6 ++---- > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > > index 52531ab28c5f..f0a1e36915b8 100644 > > --- a/drivers/gpu/drm/i915/i915_pmu.c > > +++ b/drivers/gpu/drm/i915/i915_pmu.c > > @@ -393,10 +393,8 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > > * case we assume the system is running at the intended > > * frequency. Fortunately, the read should rarely fail! > > */ > > - val = intel_rps_read_rpstat_fw(rps); > > - if (val) > > - val = intel_rps_get_cagf(rps, val); > > - else > > + val = intel_rps_get_cagf(rps, intel_rps_read_rpstat_fw(rps)); > > Will this work with gen5_invert_freq as called by intel_rps_get_cagf? PMU has ever only supported Gen6+. See intel_rps_read_rpstat_fw (Gen5 does not have a GEN6_RPSTAT1 register) as well as 01b8c2e60e96. More importantly PMU was missing support for MTL. It is to avoid these kinds of issues I have submitted a new series with a different approach which should now take care of both MTL+ as well as Gen5-: https://patchwork.freedesktop.org/series/114814/ > > + if (!val) > > val = rps->cur_freq; > > add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT], Thanks. -- Ashutosh