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From: Jani Nikula <jani.nikula@intel.com>
To: "Matt Roper" <matthew.d.roper@intel.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD
Date: Thu, 13 Jan 2022 11:06:51 +0200	[thread overview]
Message-ID: <87k0f46m38.fsf@intel.com> (raw)
In-Reply-To: <Yd+nHsmm9oKzzVDJ@mdroper-desk1.amr.corp.intel.com>

On Wed, 12 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Wed, Jan 12, 2022 at 05:09:55PM +0200, Ville Syrjälä wrote:
>> On Mon, Jan 10, 2022 at 09:15:52PM -0800, Matt Roper wrote:
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 3ef332833c4c..a4c9d2005c46 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -2858,10 +2858,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> >  #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
>> >  #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
>> >  #define   GFX_FLSH_CNTL_EN	(1 << 0)
>> > -#define ECOSKPD		_MMIO(0x21d0)
>> > -#define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
>> > -#define   ECO_GATING_CX_ONLY	(1 << 3)
>> > -#define   ECO_FLIP_DONE		(1 << 0)
>> > +#define ECOSKPD(base)		_MMIO((base) + 0x1d0)
>> > +#define   ECO_CONSTANT_BUFFER_SR_DISABLE	REG_BIT(4)
>> > +#define   ECO_GATING_CX_ONLY			REG_BIT(3)
>> > +#define   GEN6_BLITTER_FBC_NOTIFY		REG_BIT(3)
>> > +#define   ECO_FLIP_DONE				REG_BIT(0)
>> > +#define   GEN6_BLITTER_LOCK_SHIFT		16
>> 
>> This looks messy. The register contents are (mostly?) unique for
>> each engine, so this is making it rather hard to see which register
>> takes which bits. I think we should at least group the bits clearly
>> based on which engine they belong to.
>
> Makes sense.  I'll send a follow-up patch tomorrow that reorganizes this
> a bit.

For things that you're rearranging in the series, sure, please clean it
up. But for stuff already in i915_reg.h, let's not let those block this
work. Split up the file, and IMO the cleanup will be easier in the
smaller files with follow-up patches.

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-01-13  9:07 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-11  5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 01/11] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 02/11] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD Matt Roper
2022-01-12 15:09   ` Ville Syrjälä
2022-01-13  4:14     ` Matt Roper
2022-01-13  9:06       ` Jani Nikula [this message]
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 04/11] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 05/11] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h Matt Roper
2022-01-11  8:42   ` Jani Nikula
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header Matt Roper
2022-01-11 16:29   ` Lucas De Marchi
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 08/11] drm/i915: Move SNPS PHY " Matt Roper
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo " Matt Roper
2022-01-11 13:44   ` Jani Nikula
2022-01-11  5:15 ` [Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC " Matt Roper
2022-01-11 13:49   ` Jani Nikula
2022-01-11  5:16 ` [Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets Matt Roper
2022-01-11 13:50   ` Jani Nikula
2022-01-11  5:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev3) Patchwork
2022-01-11  5:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-11  6:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-11 10:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-01-11 22:17   ` Matt Roper
2022-01-11 22:19     ` Matt Roper
2022-01-12 21:41 ` [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Rodrigo Vivi
2022-01-13 16:58   ` Jani Nikula
2022-01-13 20:23     ` Rodrigo Vivi

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