From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 09/13] drm/i915: Kill off dead code from skl_dpll0_enable()
Date: Thu, 12 May 2016 13:26:36 +0300 [thread overview]
Message-ID: <87k2izh8rn.fsf@intel.com> (raw)
In-Reply-To: <1462995892-32416-10-git-send-email-ville.syrjala@linux.intel.com>
On Wed, 11 May 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We calculate the CDCLK_CTL value from scratch so no need to attempt
> some form of RMW first.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0186f775f353..a21f9d3fb869 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5566,17 +5566,12 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
> u32 val;
>
> /* select the minimum CDCLK before enabling DPLL 0 */
> - val = I915_READ(CDCLK_CTL);
> - val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
> - val |= CDCLK_FREQ_337_308;
> -
> if (required_vco == 8640)
> min_freq = 308570;
> else
> min_freq = 337500;
>
> val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
> -
> I915_WRITE(CDCLK_CTL, val);
> POSTING_READ(CDCLK_CTL);
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2016-05-12 10:26 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-11 19:44 [PATCH 00/13] drm/i915: cdclk code cleanup ville.syrjala
2016-05-11 19:44 ` [PATCH 01/13] drm/i915: Drop checks for max_pixclk failures in cdclk computation ville.syrjala
2016-05-12 10:02 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 02/13] drm/i915: Extract broadwell_calc_cdclk() ville.syrjala
2016-05-12 10:03 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 03/13] drm/i915: Untangle .fdi_link_train and cdclk vfunc setup ville.syrjala
2016-05-12 10:06 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 04/13] drm/i915: Don't pass dev_priv to broxton_calc_cdclk() ville.syrjala
2016-05-12 10:07 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 05/13] drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation ville.syrjala
2016-05-12 10:13 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 06/13] drm/i915: Use skl_cdclk_decimal() on bxt ville.syrjala
2016-05-12 10:23 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 07/13] drm/i915: Remove 10% cdclk guardband on BXT ville.syrjala
2016-05-12 16:42 ` Imre Deak
2016-05-11 19:44 ` [PATCH 08/13] drm/i915: Extract skl_dpll0_disable() ville.syrjala
2016-05-12 10:25 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 09/13] drm/i915: Kill off dead code from skl_dpll0_enable() ville.syrjala
2016-05-12 10:26 ` Jani Nikula [this message]
2016-05-11 19:44 ` [PATCH 10/13] drm/i915: s/freq/cdclk/ ville.syrjala
2016-05-12 10:28 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 11/13] drm/i915: s/required_vco/vco/ in skl cdclk code ville.syrjala
2016-05-12 10:29 ` Jani Nikula
2016-05-11 19:44 ` [PATCH 12/13] drm/i915: Program BXT_CDCLK_CD2X_PIPE ville.syrjala
2016-05-12 16:58 ` Imre Deak
2016-05-11 19:44 ` [PATCH 13/13] drm/i915: Eliminate the CDCLK_CTL RMW on BXT ville.syrjala
2016-05-12 17:05 ` Imre Deak
2016-05-11 20:23 ` ✗ Ro.CI.BAT: failure for drm/i915: cdclk code cleanup Patchwork
2016-05-12 15:16 ` Ville Syrjälä
2016-05-13 18:42 ` [PATCH 00/13] " Ville Syrjälä
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