Re: [PATCH 31/49] drm/i915/bxt: add description about the BXT PHYs

Ville Syrjälä
2015-03-19T17:30:20Z

On Tue, Mar 17, 2015 at 11:39:57AM +0200, Imre Deak wrote:
> Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> Documentation/DocBook/drm.tmpl | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++++---
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> index 7a45775..327757f 100644
> --- a/Documentation/DocBook/drm.tmpl
> +++ b/Documentation/DocBook/drm.tmpl
> @@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
> DPIO
> !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
>
> - Dual channel PHY (VLV/CHV)
> + Dual channel PHY (VLV/CHV/BXT)
> <tgroup cols="8">
> <colspec colname="c0" />
> <colspec colname="c1" />
> @@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
> </tgroup>
>
>
> - Single channel PHY (CHV)
> + Single channel PHY (CHV/BXT)
> <tgroup cols="4">
> <colspec colname="c0" />
> <colspec colname="c1" />
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a3579c0..95532b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -718,7 +718,7 @@ enum skl_disp_power_wells {
> /**
> * DOC: DPIO
> *
> - * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
> + * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
> * ports. DPIO is the name given to such a display PHY. These PHYs
> * don't follow the standard programming model using direct MMIO
> * registers, and instead their registers must be accessed trough IOSF
> @@ -773,9 +773,13 @@ enum skl_disp_power_wells {
> *
> * Note: digital port B is DDI0, digital port C is DDI1,
> * digital port D is DDI2
> + *
> + * On BXT the above mappings apply for both the dual and single channel PHY,
> + * with the difference that any of the three ports can connect to any of the
> + * three pipes. Also the single channel PHY is used for port A (DDI2/EDP).

I think we might need to split the VLV/CHV vs. BXT descriptions a bit
more. The pipe->CMN/PLL/REF port->PCS/TX rule doesn't seem to hold
anymore due to the more flexible pipe<->port mapping.

So maybe something like:
"
Generally on VLV/CHV the common lane...
...
port D == PCS/TX CH0

On BXT the entire PHY channel corresponds to the port. That means
the PLL is also now associated with the port rather than the pipe,
and so the clock needs to be routed to the appropriate transcoder.
Port A PLL is directly connected to transcoder EDP and port B/C
PLLs can be routed to any transcoder A/B/C.
"

Also maybe reverse the DDI<->port mapping note to make it simpler. Eg:

"Note: DDI0 is digital port B, DDI1 is digital port C, and
DDI2 is digital port D (CHV) or port A (BXT)."

> */
> /*
> - * Dual channel PHY (VLV/CHV)
> + * Dual channel PHY (VLV/CHV/BXT)
> * ---------------------------------
> * | CH0 | CH1 |
> * | CMN/PLL/REF | CMN/PLL/REF |
> @@ -787,7 +791,7 @@ enum skl_disp_power_wells {
> * | DDI0 | DDI1 | DP/HDMI ports
> * ---------------------------------
> *
> - * Single channel PHY (CHV)
> + * Single channel PHY (CHV/BXT)
> * -----------------
> * | CH0 |
> * | CMN/PLL/REF |
> --
> 2.1.0
>
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--
Ville Syrjälä
Intel OTC