Re: [PATCH 02/49] drm/i915/bxt: BXT FBC enablement

Rodrigo Vivi
2015-03-17T17:49:47Z

Does BXT really has fbc? And same implementation and registers as HSW?

On Tue, Mar 17, 2015 at 2:39 AM, Imre Deak <imre.deak@intel.com> wrote:
> From: Daisy Sun <daisy.sun@intel.com>
>
> Enable FBC feature on Broxton
>
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun <daisy.sun@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4d50785..48434cb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -388,6 +388,7 @@ static const struct intel_device_info intel_broxton_info = {
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> .num_pipes = 3,
> .has_ddi = 1,
> + .has_fbc = 1,
> GEN_DEFAULT_PIPEOFFSETS,
> IVB_CURSOR_OFFSETS,
> };
> --
> 2.1.0
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br