Re: [PATCH 11/49] drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE

Daniel Vetter
2015-03-17T10:33:29Z

On Tue, Mar 17, 2015 at 11:39:37AM +0200, Imre Deak wrote:
> On GEN9+ per specification a NULL PIPE_CONTROL needs to be emitted
> before any PIPE_CONTROL command with the VS_INVALIDATE flag set.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Can you please take out the gen9/skl patches from your bxt enabling into a
separate series so that we can fastrack it?

Thanks, Daniel

> ---
> drivers/gpu/drm/i915/intel_lrc.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index fcb074b..71aeeb3 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1262,6 +1262,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
> {
> struct intel_engine_cs *ring = ringbuf->ring;
> u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + bool vf_flush_wa;
> u32 flags = 0;
> int ret;
>
> @@ -1283,10 +1284,26 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
> flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> }
>
> - ret = intel_logical_ring_begin(ringbuf, ctx, 6);
> + /*
> + * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
> + * control.
> + */
> + vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
> + flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
> +
> + ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
> if (ret)
> return ret;
>
> + if (vf_flush_wa) {
> + intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> + intel_logical_ring_emit(ringbuf, 0);
> + intel_logical_ring_emit(ringbuf, 0);
> + intel_logical_ring_emit(ringbuf, 0);
> + intel_logical_ring_emit(ringbuf, 0);
> + intel_logical_ring_emit(ringbuf, 0);
> + }
> +
> intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> intel_logical_ring_emit(ringbuf, flags);
> intel_logical_ring_emit(ringbuf, scratch_addr);
> --
> 2.1.0
>
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--
Daniel Vetter
Software Engineer, Intel Corporation