[PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

Imre Deak
2015-03-17T09:40:47Z

From: Vandana Kannan <vandana.kannan@intel.com>

Add display clock/PHY initialization sequence as per BSpec.

Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
value with 624 MHz and returning 0 in case it exceeds.

Note that the CD clock and PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
This also means that atm dynamic power gating power well #2 is
effectively disabled.

v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set

v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
"Check CDCLK upper limit" patches
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY_A and PHY_BC, instead of open-coding the same

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 126 +++++++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 291 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 75 +++++++++
drivers/gpu/drm/i915/intel_drv.h | 4 +
4 files changed, 496 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4474d3..a3579c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1120,6 +1120,110 @@ enum skl_disp_power_wells {
#define DPIO_FRC_LATENCY_SHFIT 8
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
#define DPIO_UPAR_SHIFT 30
+
+/* BXT PHY registers */
+enum bxt_phy {
+ BXT_PHY_A,
+ BXT_PHY_BC
+};
+
+#define BXT_PHY(phy, a, b) ((a) + (phy) * ((b) - (a)))
+
+#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR 0x138090
+#define _EDP_POWER_ON (1 << 1)
+#define _DDI_POWER_ON (1 << 0)
+#define GT_DISPLAY_POWER_ON(phy) BXT_PHY(phy, _EDP_POWER_ON, \
+ _DDI_POWER_ON)
+
+#define _PHY_CTL_FAMILY_EDP 0x64C80
+#define _PHY_CTL_FAMILY_DDI 0x64C90
+#define COMMON_RESET_DIS (1 << 31)
+#define BXT_PHY_CTL_FAMILY(phy) BXT_PHY(phy, _PHY_CTL_FAMILY_EDP, \
+ _PHY_CTL_FAMILY_DDI)
+
+/* BXT PHY common lane registers */
+#define _PORT_CL1CM_DW0_A 0x162000
+#define _PORT_CL1CM_DW0_BC 0x6C000
+#define PHY_POWER_GOOD (1 << 16)
+#define BXT_PORT_CL1CM_DW0(phy) BXT_PHY(phy, _PORT_CL1CM_DW0_A, \
+ _PORT_CL1CM_DW0_BC)
+
+#define _PORT_CL1CM_DW9_A 0x162024
+#define _PORT_CL1CM_DW9_BC 0x6C024
+#define IREF0RC_OFFSET_SHIFT 8
+#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW9(phy) BXT_PHY(phy, _PORT_CL1CM_DW9_A, \
+ _PORT_CL1CM_DW9_BC)
+
+#define _PORT_CL1CM_DW10_A 0x162028
+#define _PORT_CL1CM_DW10_BC 0x6C028
+#define IREF1RC_OFFSET_SHIFT 8
+#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW10(phy) BXT_PHY(phy, _PORT_CL1CM_DW10_A, \
+ _PORT_CL1CM_DW10_BC)
+
+#define _PORT_CL1CM_DW28_A 0x162070
+#define _PORT_CL1CM_DW28_BC 0x6C070
+#define OCL1_POWER_DOWN_EN (1 << 23)
+#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
+#define SUS_CLK_CONFIG 0x3
+#define BXT_PORT_CL1CM_DW28(phy) BXT_PHY(phy, _PORT_CL1CM_DW28_A, \
+ _PORT_CL1CM_DW28_BC)
+
+#define _PORT_CL1CM_DW30_A 0x162078
+#define _PORT_CL1CM_DW30_BC 0x6C078
+#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
+#define BXT_PORT_CL1CM_DW30(phy) BXT_PHY(phy, _PORT_CL1CM_DW30_A, \
+ _PORT_CL1CM_DW30_BC)
+
+/* Defined for PHY_BC only */
+#define BXT_PORT_CL2CM_DW6_BC 0x6C358
+#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
+
+/* BXT PHY Ref registers */
+#define _PORT_REF_DW3_A 0x16218C
+#define _PORT_REF_DW3_BC 0x6C18C
+#define GRC_DONE (1 << 22)
+#define BXT_PORT_REF_DW3(phy) BXT_PHY(phy, _PORT_REF_DW3_A, \
+ _PORT_REF_DW3_BC)
+
+#define _PORT_REF_DW6_A 0x162198
+#define _PORT_REF_DW6_BC 0x6C198
+/*
+ * FIXME: BSpec disagrees on the following two fields, check them with
+ * HW/documentation people.
+ */
+#define GRC_CODE_SHIFT 23
+#define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT)
+#define GRC_CODE_FAST_SHIFT 16
+#define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT)
+#define GRC_CODE_SLOW_SHIFT 8
+#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
+#define GRC_CODE_NOM_MASK 0xFF
+#define BXT_PORT_REF_DW6(phy) BXT_PHY(phy, _PORT_REF_DW6_A, \
+ _PORT_REF_DW6_BC)
+
+#define _PORT_REF_DW8_A 0x1621A0
+#define _PORT_REF_DW8_BC 0x6C1A0
+#define GRC_DIS (1 << 15)
+#define GRC_RDY_OVRD (1 << 1)
+#define BXT_PORT_REF_DW8(phy) BXT_PHY(phy, _PORT_REF_DW8_A, \
+ _PORT_REF_DW8_BC)
+
+/* BXT PHY TX registers */
+#define BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
+ ((lane) & 1) * 0x80)
+
+#define _PORT_TX_DW14_LN0_A 0x162538
+#define _PORT_TX_DW14_LN0_B 0x6C538
+#define _PORT_TX_DW14_LN0_C 0x6C938
+#define LATENCY_OPTIM_SHIFT 30
+#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
+#define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3(port, _PORT_TX_DW14_LN0_A, \
+ _PORT_TX_DW14_LN0_B, \
+ _PORT_TX_DW14_LN0_C) + \
+ BXT_LANE_OFFSET(lane))
+
/*
* Fence registers
*/
@@ -5326,6 +5430,9 @@ enum skl_disp_power_wells {
#define DISP_FBC_WM_DIS (1<<15)
#define DISP_ARB_CTL2 0x45004
#define DISP_DATA_PARTITION_5_6 (1<<6)
+#define DBUF_CTL 0x45008
+#define DBUF_POWER_REQUEST (1<<31)
+#define DBUF_POWER_STATE (1<<30)
#define GEN7_MSG_CTL 0x45010
#define WAIT_FOR_PCH_RESET_ACK (1<<1)
#define WAIT_FOR_PCH_FLR_ACK (1<<0)
@@ -6271,6 +6378,7 @@ enum skl_disp_power_wells {
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
+#define DISPLAY_PCU_CONTROL 0x17
#define DISPLAY_IPS_CONTROL 0x19
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA 0x138128
@@ -6748,6 +6856,13 @@ enum skl_disp_power_wells {
#define CDCLK_FREQ_675_617 (3<<26)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)

+#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
+#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
+#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
+#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
+#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
+#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
+
/* LCPLL_CTL */
#define LCPLL1_CTL 0x46010
#define LCPLL2_CTL 0x46014
@@ -6812,6 +6927,17 @@ enum skl_disp_power_wells {
#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)

+/* BXT display engine PLL */
+#define BXT_DE_PLL_CTL 0x6d000
+#define BXT_DE_PLL_RATIO_1152 0x3c
+#define BXT_DE_PLL_RATIO_1248 0x41
+#define BXT_DE_PLL_RATIO_DEFAULT 0x64
+#define BXT_DE_PLL_RATIO_MASK 0x7f
+
+#define BXT_DE_PLL_ENABLE 0x46070
+#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
+#define BXT_DE_PLL_LOCK (1 << 30)
+
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
* since on HSW we can't write to it using I915_WRITE. */
#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a203d9d..789682d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1957,6 +1957,294 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
}
}

+static void bxt_init_phy(struct drm_i915_private *dev_priv, enum bxt_phy phy)
+{
+ enum port port;
+ uint32_t val;
+
+ val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
+ val |= GT_DISPLAY_POWER_ON(phy);
+ I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, val);
+
+ /* Considering 10ms timeout until BSpec is updated */
+ if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+ DRM_ERROR("timeout during PHY#%d power on\n", phy);
+
+ /* Program latency optim setting */
+ for (port = (phy == BXT_PHY_A ? PORT_A : PORT_B);
+ port <= (phy == BXT_PHY_A ? PORT_A : PORT_C); port++) {
+ int lane;
+
+ for (lane = 0; lane < 4; lane++) {
+ val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
+ val &= ~LATENCY_OPTIM;
+ if (lane == 1)
+ val |= LATENCY_OPTIM;
+
+ I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
+ }
+ }
+
+ /* Program PLL Rcomp code offset */
+ val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
+ val &= ~IREF0RC_OFFSET_MASK;
+ val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
+ I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
+
+ val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
+ val &= ~IREF1RC_OFFSET_MASK;
+ val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
+ I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
+
+ /* Program power gating */
+ val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
+ val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
+ SUS_CLK_CONFIG;
+ I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
+
+ if (phy == BXT_PHY_BC) {
+ val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
+ val |= DW6_OLDO_DYN_PWR_DOWN_EN;
+ I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
+ }
+
+ val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
+ val &= ~OCL2_LDOFUSE_PWR_DIS;
+ /*
+ * On PHY_A disable power on the second channel, since no port is
+ * connected there. On PHY_BC both channels have a port, so leave it
+ * enabled.
+ * Note that port C is only connected on BXT-P, so on BXT0/1 we should
+ * power down the second channel on PHY_BC as well.
+ */
+ if (phy == BXT_PHY_A)
+ val |= OCL2_LDOFUSE_PWR_DIS;
+ I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
+
+ if (phy == BXT_PHY_BC) {
+ uint32_t grc_code;
+ /*
+ * PHY_BC isn't connected to an RCOMP resistor so copy over
+ * the corresponding calibrated value from PHY_A, and disable
+ * the automatic calibration on PHY_BC.
+ */
+ if (wait_for(I915_READ(BXT_PORT_REF_DW3(BXT_PHY_A)) & GRC_DONE,
+ 10))
+ DRM_ERROR("timeout waiting for PHY#0 GRC\n");
+
+ val = I915_READ(BXT_PORT_REF_DW6(BXT_PHY_A));
+ val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+ grc_code = val << GRC_CODE_FAST_SHIFT |
+ val << GRC_CODE_SLOW_SHIFT |
+ val;
+ I915_WRITE(BXT_PORT_REF_DW6(BXT_PHY_BC), grc_code);
+
+ val = I915_READ(BXT_PORT_REF_DW8(BXT_PHY_BC));
+ val |= GRC_DIS | GRC_RDY_OVRD;
+ I915_WRITE(BXT_PORT_REF_DW8(BXT_PHY_BC), val);
+ }
+
+ /* Release common_reset */
+ val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
+ val |= COMMON_RESET_DIS;
+ I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
+}
+
+void bxt_ddi_phy_init(struct drm_device *dev)
+{
+ /* Enable PHY_A first since it provides Rcomp for PHY_BC */
+ bxt_init_phy(dev->dev_private, BXT_PHY_A);
+ bxt_init_phy(dev->dev_private, BXT_PHY_BC);
+}
+
+static void bxt_ddi_phy_uninit(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t temp;
+
+ temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_A));
+ I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_A), temp & ~COMMON_RESET_DIS);
+
+ temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_BC));
+ I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_BC), temp & ~COMMON_RESET_DIS);
+
+ I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, 0);
+}
+
+/*
+ * It is the responsibility of the caller to ensure that
+ * criteria for changing the CD clk frequency is met.
+ *
+ * This function only changes CD clock frequency.
+ * TODO:- 1. Add functions to change only the divider and
+ * 2. call impacted functions like backlight, WiDi, watermark.
+*/
+void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t cdclk_ctl, decimal, ratio;
+ uint32_t divider, freq, current_freq;
+ int ret;
+
+ freq = (frequency / 1000 - 1) * 2;
+ decimal = DIV_ROUND_UP(frequency, 25000);
+
+ switch (frequency) {
+ case 144000:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_4;
+ ratio = BXT_DE_PLL_RATIO_1152;
+ break;
+ case 288000:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+ ratio = BXT_DE_PLL_RATIO_1152;
+ break;
+ case 384000:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
+ ratio = BXT_DE_PLL_RATIO_1152;
+ break;
+ case 576000:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+ ratio = BXT_DE_PLL_RATIO_1152;
+ break;
+ case 624000:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+ ratio = BXT_DE_PLL_RATIO_1248;
+ break;
+ case 0:
+ /* Incase incoming frequency is 0, only DE PLL has to be
+ * disabled, divider/ratio need not be programmed.
+ * Hence, initializing to 0.
+ */
+ divider = ratio = 0;
+ break;
+ default:
+ DRM_ERROR("Unsupported cd frequency %d enable request",
+ frequency);
+ return;
+ }
+
+ current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
+ current_freq = ((current_freq / 2) + 1) * 1000;
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+ /* Inform power controller of upcoming frequency change */
+ ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
+ 0x80000000);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ if (ret) {
+ DRM_DEBUG_KMS("pcode write failed, leaving CDCLK unchanged (%d)\n",
+ ret);
+ return;
+ }
+
+ /* DE PLL has to be disabled when input frequency is 0 or
+ * frequency is to be changed to 624MHz or changed from 624 MHz
+ */
+ if (!frequency || current_freq == 624000 || frequency == 624000) {
+ I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
+ WARN(wait_for(
+ !(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
+ 1), "DE PLL locked\n");
+ }
+
+ if (frequency) {
+ I915_WRITE(BXT_DE_PLL_CTL, ratio);
+ I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
+ WARN(wait_for(
+ I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1),
+ "DE PLL not locked\n");
+
+ cdclk_ctl = I915_READ(CDCLK_CTL);
+ cdclk_ctl &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
+ cdclk_ctl |= divider;
+
+ /* Disable SSA Precharge when CD clock frequency < 500 MHz,
+ * enable otherwise.
+ */
+ cdclk_ctl &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+ if (frequency >= 500000)
+ cdclk_ctl |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+ cdclk_ctl &= ~CDCLK_FREQ_DECIMAL_MASK;
+ cdclk_ctl |= freq;
+ I915_WRITE(CDCLK_CTL, cdclk_ctl);
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+ ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
+ decimal);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ if (ret) {
+ DRM_DEBUG_KMS("pcode write failed. err = %d decimal = %d\n",
+ ret, decimal);
+ return;
+ }
+
+ dev_priv->cdclk_freq = frequency;
+ } else {
+ mutex_lock(&dev_priv->rps.hw_lock);
+ ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL, 1);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ if (ret)
+ DRM_DEBUG_KMS("pcode write failed. err = %d decimal = 1\n",
+ ret);
+ }
+}
+
+void bxt_init_cdclk(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
+ * or else the reset will hang because there is no PCH to respond.
+ * Move the handshake programming to initialization sequence.
+ * Previously was left up to BIOS.
+ */
+ u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
+
+ temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
+ I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
+
+ /* Enable PG1 for cdclk */
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
+ /* check if cd clock is enabled */
+ if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
+ DRM_DEBUG_KMS("Display already initialized\n");
+ return;
+ }
+
+ /* FIXME:- The initial CDCLK needs to be read from VBT.
+ * Need to make this change after VBT has changes for BXT.
+ */
+ bxt_select_cdclk_freq(dev, 624000);
+
+ I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
+ udelay(10);
+
+ if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
+ DRM_ERROR("DBuf power enable timeout!\n");
+}
+
+void bxt_uninit_cdclk(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ bxt_ddi_phy_uninit(dev);
+
+ I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
+ udelay(10);
+
+ if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
+ DRM_ERROR("DBuf power disable timeout!\n");
+
+ bxt_select_cdclk_freq(dev, 0);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
+}
+
void intel_ddi_pll_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1973,6 +2261,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
if (IS_SKYLAKE(dev)) {
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
DRM_ERROR("LCPLL1 is disabled\n");
+ } else if (IS_BROXTON(dev)) {
+ bxt_init_cdclk(dev);
+ bxt_ddi_phy_init(dev);
} else {
/*
* The LCPLL register should be turned on by the BIOS. For now
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b91862e..ba2d1ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8284,6 +8284,75 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
intel_prepare_ddi(dev);
}

+static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
+ int max_pixclk)
+{
+ /*
+ * CDclks are supported:
+ * 144MHz
+ * 288MHz
+ * 384MHz
+ * 576MHz
+ * 624MHz
+ * Check to see whether we're above 90% of the lower bin and
+ * adjust if needed.
+ */
+
+ /* If max_pixclk is greater than the max allowed clock, return 0.
+ * FIXME:- The max clock allowed needs to be provided by GOP/VBIOS
+ * via a scratch pad register. Till that is enabled, use 624MHz as max.
+ */
+ if (max_pixclk > 624000)
+ return 0;
+ else if (max_pixclk > 576000*9/10)
+ return 624000;
+ else if (max_pixclk > 384000*9/10)
+ return 576000;
+ else if (max_pixclk > 288000*9/10)
+ return 384000;
+ else if (max_pixclk > 144000*9/10)
+ return 288000;
+ else
+ return 144000;
+}
+
+static void broxton_modeset_global_pipes(struct drm_device *dev,
+ unsigned *prepare_pipes)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc;
+ int max_pixclk = intel_mode_max_pixclk(dev_priv);
+ int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
+
+ if (!req_cdclk) {
+ DRM_ERROR("CDCLK exceeds maximum allowable value\n");
+ return;
+ }
+
+ if (req_cdclk == dev_priv->cdclk_freq)
+ return;
+
+ /* disable/enable all currently active pipes while we change cdclk */
+ for_each_intel_crtc(dev, intel_crtc)
+ if (intel_crtc->base.enabled)
+ *prepare_pipes |= (1 << intel_crtc->pipe);
+}
+
+static void broxton_modeset_global_resources(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int max_pixclk = intel_mode_max_pixclk(dev_priv);
+ int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
+
+ if (!req_cdclk) {
+ DRM_ERROR("CDCLK exceeds maximum allowable value\n");
+ return;
+ }
+
+ if (req_cdclk != dev_priv->cdclk_freq)
+ bxt_select_cdclk_freq(dev, req_cdclk);
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -11239,6 +11308,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,

/* may have added more to prepare_pipes than we should */
prepare_pipes &= ~disable_pipes;
+ } else if (IS_BROXTON(dev)) {
+ broxton_modeset_global_pipes(dev, &prepare_pipes);
+ prepare_pipes &= ~disable_pipes;
}

ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
@@ -13133,6 +13205,9 @@ static void intel_init_display(struct drm_device *dev)
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.modeset_global_resources =
valleyview_modeset_global_resources;
+ } else if (IS_BROXTON(dev)) {
+ dev_priv->display.modeset_global_resources =
+ broxton_modeset_global_resources;
}

switch (INTEL_INFO(dev)->gen) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c77128c..4bc2041 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -873,6 +873,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
+void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency);

/* intel_frontbuffer.c */
void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
@@ -1020,6 +1021,9 @@ void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
+void bxt_init_cdclk(struct drm_device *dev);
+void bxt_uninit_cdclk(struct drm_device *dev);
+void bxt_ddi_phy_init(struct drm_device *dev);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
--
2.1.0