From mboxrd@z Thu Jan 1 00:00:00 1970 From: Francisco Jerez Subject: Re: [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings. Date: Mon, 05 Jan 2015 05:03:16 +0200 Message-ID: <87k312gc97.fsf@riseup.net> References: <1420419950-3135-1-git-send-email-zhigang.gong@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0839748301==" Return-path: Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTP id CE2976E13A for ; Sun, 4 Jan 2015 19:06:28 -0800 (PST) In-Reply-To: <1420419950-3135-1-git-send-email-zhigang.gong@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Zhigang Gong List-Id: intel-gfx@lists.freedesktop.org --===============0839748301== Content-Type: multipart/signed; boundary="==-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --==-=-= Content-Type: multipart/mixed; boundary="=-=-=" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Zhigang Gong writes: > According to bspec, ROW_CHICKEN3's bit 6 which is to disable > move of cacheable global atomics to L3 is needed for GT3 D > stepping. > > I enabled it and tested it with HSW GT2 D stepping and GT3 E stepping. > The atomics works fine in beignet. And it could get more than 10x perform= ance > improvement with some workload, for an example, the "splat" kernel in dar= ktable, > without this patch, it consumes 50 seconds in one large raw picture proce= ssing. > But with this patch, the same process only takes less than 1 second. > I tried this already (on HSW GT2 D as well) and I don't think it's enough to get L3 atomics working reliably. Even though they did seem to work OK at first glance I observed some corruption issues (e.g. atomic writes not landing in system memory) when doing atomic writes to contiguous (as in within the same cache-line) locations in memory. The "unused" ARB_shader_image_load_store test [1] I sent to the Piglit mailing list some time ago exposes this IIRC, and probably a couple of other tests too. Also this change is going to cause an instant lock-up anytime Mesa uses atomics because Mesa doesn't change the default L3 way allocation for the DC, which turns out to be 0 on HSW. [1] http://lists.freedesktop.org/archives/piglit/2014-December/013571.html > Signed-off-by: Zhigang Gong > --- > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 7d99a9c..8a27802 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5938,10 +5938,12 @@ static void haswell_init_clock_gating(struct drm_= device *dev) >=20=20 > ilk_init_lp_watermarks(dev); >=20=20 > - /* L3 caching of data atomics doesn't work -- disable it. */ > - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); > - I915_WRITE(HSW_ROW_CHICKEN3, > - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); > + if (IS_HSW_GT3(dev) && dev->pdev->revision <=3D 6) { > + /* L3 caching of data atomics doesn't work -- disable it. */ > + I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); > + I915_WRITE(HSW_ROW_CHICKEN3, > + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); > + } >=20=20 > /* This is required by WaCatErrorRejectionIssue:hsw */ > I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, > --=20 > 1.8.3.2 --=-=-=-- --==-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iF4EAREIAAYFAlSp/vQACgkQg5k4nX1Sv1sfJwD9HQZIry0iVEZ+e1Bwt4uEPKTm WPUb33xSNOOg+YLoMkwA/2stSGDMwKa1j9CSkZNRLyroH/4I2KgKyHgHeFSET5FG =te3t -----END PGP SIGNATURE----- --==-=-=-- --===============0839748301== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK --===============0839748301==--