Re: [PATCH 22/89] drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylake

Rodrigo Vivi
2014-09-17T01:16:30Z

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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Thu, Sep 4, 2014 at 4:26 AM, Damien Lespiau <damien.lespiau@intel.com>
wrote:

> Skylake doesn't use the pre-charge field now, but, instead, we need to
> specify the total number of SYNC pulses for the SYNC phase (pre-charge +
> SYNC pattern pules). Let's use the default value (32) for that.
>
> v3: increase DP AUX TX timeout as 400us is not to be used on SKL
> apparently (Jesse).
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 20 +++++++++++++++++++-
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 087085c..acd0a7b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3630,6 +3630,7 @@ enum punit_power_well {
> #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
> #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
> #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
> +#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
>
> /*
> * Computing GMCH M and N values for the Display Port link
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 4560ced..5755f59 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -529,6 +529,21 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
> *intel_dp,
> (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
> }
>
> +static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> + bool has_aux_irq,
> + int send_bytes,
> + uint32_t unused)
> +{
> + return DP_AUX_CH_CTL_SEND_BUSY |
> + DP_AUX_CH_CTL_DONE |
> + (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
> + DP_AUX_CH_CTL_TIME_OUT_ERROR |
> + DP_AUX_CH_CTL_TIME_OUT_1600us |
> + DP_AUX_CH_CTL_RECEIVE_ERROR |
> + (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> +}
> +
> static int
> intel_dp_aux_ch(struct intel_dp *intel_dp,
> uint8_t *send, int send_bytes,
> @@ -4747,7 +4762,10 @@ intel_dp_init_connector(struct intel_digital_port
> *intel_dig_port,
> else
> intel_dp->get_aux_clock_divider =
> i9xx_get_aux_clock_divider;
>
> - intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
> + if (INTEL_INFO(dev)->gen >= 9)
> + intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
> + else
> + intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
>
> /* Preserve the current hw state. */
> intel_dp->DP = I915_READ(intel_dp->output_reg);
> --
> 1.8.3.1
>
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>

--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

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