From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915: Enable pixel replicated modes on BDW and HSW. Date: Wed, 24 Sep 2014 11:19:17 +0300 Message-ID: <87k34tmnwa.fsf@intel.com> References: <1411495616-21883-1-git-send-email-clinton.a.taylor@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 83CFD6E4AB for ; Wed, 24 Sep 2014 01:19:19 -0700 (PDT) In-Reply-To: <1411495616-21883-1-git-send-email-clinton.a.taylor@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: clinton.a.taylor@intel.com, Intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 23 Sep 2014, clinton.a.taylor@intel.com wrote: > From: Clint Taylor > > Haswell and later silicon has added a new pixel replication register > to the pipe timings for each transcoder. Now in addition to the > DPLL_A_MD register for the pixel clock double, we also need to write to > the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing > to the DPLL only double the pixel clock. Any idea of the failure modes that this will fix? I'm wondering if we already have bugs for this. BR, Jani. > > Signed-off-by: Clint Taylor > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_display.c | 6 +++++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 15c0eaa..7c078d9 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2431,6 +2431,7 @@ enum punit_power_well { > #define _PIPEASRC 0x6001c > #define _BCLRPAT_A 0x60020 > #define _VSYNCSHIFT_A 0x60028 > +#define _MULTIPLY_A 0x6002c > > /* Pipe B timing regs */ > #define _HTOTAL_B 0x61000 > @@ -2442,6 +2443,7 @@ enum punit_power_well { > #define _PIPEBSRC 0x6101c > #define _BCLRPAT_B 0x61020 > #define _VSYNCSHIFT_B 0x61028 > +#define _MULTIPLY_B 0x6102c > > #define TRANSCODER_A_OFFSET 0x60000 > #define TRANSCODER_B_OFFSET 0x61000 > @@ -2462,6 +2464,7 @@ enum punit_power_well { > #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) > #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) > #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) > +#define MULTIPLY(trans) _TRANSCODER2(trans, _MULTIPLY_A) > > /* HSW+ eDP PSR registers */ > #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index c092ff4..e58fcde 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4152,6 +4152,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > > intel_set_pipe_timings(intel_crtc); > > + I915_WRITE(MULTIPLY(intel_crtc->config.cpu_transcoder), > + intel_crtc->config.pixel_multiplier - 1); > + > if (intel_crtc->config.has_pch_encoder) { > intel_cpu_transcoder_set_m_n(intel_crtc, > &intel_crtc->config.fdi_m_n, NULL); > @@ -7811,7 +7814,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && > (I915_READ(IPS_CTL) & IPS_ENABLE); > > - pipe_config->pixel_multiplier = 1; > + pipe_config->pixel_multiplier = > + I915_READ(MULTIPLY(pipe_config->cpu_transcoder)) + 1; > > return true; > } > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center