From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915/chv: WaDisablePwrmtrEvent:chv on CHV only Date: Tue, 10 Jun 2014 18:30:54 +0300 Message-ID: <87k38ou6hd.fsf@intel.com> References: <1402333609-5782-1-git-send-email-Tom.O'Rourke@intel.com> <20140609173238.GA27756@strange.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 289B46E6E7 for ; Tue, 10 Jun 2014 08:31:02 -0700 (PDT) In-Reply-To: <20140609173238.GA27756@strange.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau , Tom.O'Rourke@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 09 Jun 2014, Damien Lespiau wrote: > On Mon, Jun 09, 2014 at 10:06:49AM -0700, Tom.O'Rourke@intel.com wrote: >> From: Tom O'Rourke >> >> In gen8_enable_rps, don't write CHV registers unless IS_CHERRYVIEW. >> >> Signed-off-by: Tom O'Rourke > > A lovely catch. Sadly gen8_enable_rps does not get called on chv, so the fix is wrong. BR, Jani. > > Reviewed-by: Damien Lespiau > > -- > Damien > >> --- >> drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- >> 1 file changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index d9c5918..3d3e402 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -3522,8 +3522,10 @@ static void gen8_enable_rps(struct drm_device *dev) >> I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); >> >> /* WaDisablePwrmtrEvent:chv (pre-production hw) */ >> - I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); >> - I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); >> + if (IS_CHERRYVIEW(dev)) { >> + I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); >> + I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); >> + } >> >> /* 5: Enable RPS */ >> I915_WRITE(GEN6_RP_CONTROL, >> -- >> 1.7.9.5 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center