From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: Re: [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+. Date: Mon, 26 Sep 2011 15:25:29 -0700 Message-ID: <87k48v2b6u.fsf@eliezer.anholt.net> References: <1317063563-1526-1-git-send-email-kenneth@whitecape.org> <20110926203156.GE2804@phenom.ffwll.local> <4E80E2C2.3000904@whitecape.org> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0751198880==" Return-path: In-Reply-To: <4E80E2C2.3000904@whitecape.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Kenneth Graunke , Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0751198880== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Mon, 26 Sep 2011 13:38:26 -0700, Kenneth Graunke = wrote: > On 09/26/2011 01:31 PM, Daniel Vetter wrote: > > On Mon, Sep 26, 2011 at 11:59:23AM -0700, Kenneth Graunke wrote: > >> +static int > >> +gen6_render_ring_flush(struct intel_ring_buffer *ring, > >> + u32 invalidate_domains, u32 flush_domains) > >> +{ > >> + u32 flags =3D 0; > >> + struct pipe_control *pc =3D ring->private; > >> + u32 scratch_addr =3D pc->gtt_offset + 128; > >> + int ret; > >> + > >> + /* Force SNB workarounds for PIPE_CONTROL flushes */ > >> + intel_emit_post_sync_nonzero_flush(ring); > >> + > >> + /* Just flush everything for now */ > >> + flags |=3D PIPE_CONTROL_WC_FLUSH; > >> + flags |=3D PIPE_CONTROL_IS_FLUSH; > >> + flags |=3D PIPE_CONTROL_TC_FLUSH; > >> + flags |=3D PIPE_CONTROL_DEPTH_FLUSH; > >> + flags |=3D PIPE_CONTROL_VFC; > >=20 > > Any reason you're not also setting the constant cache and state cache > > invalidate bits? > > -Daniel >=20 > Bits 2 and 3? No particular reason; perhaps they should be. IIRC we're not using the constant cache today, but it would be nice to, so let's get it set. We definitely need state cache invalidate. --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iEYEARECAAYFAk6A+9kACgkQHUdvYGzw6veEaQCfYqdNUpnt/bqjMm/rGfZNGpCz gHYAnA5xZwX8xYKUb6MVV6XBWC+y4nvx =psTM -----END PGP SIGNATURE----- --=-=-=-- --===============0751198880== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0751198880==--