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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Arun R Murthy <arun.r.murthy@intel.com>,
	intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Arun R Murthy <arun.r.murthy@intel.com>
Subject: Re: [PATCHv2] drm/i915/display: BMG supports UHBR13.5
Date: Thu, 29 Aug 2024 15:19:37 +0300	[thread overview]
Message-ID: <87le0fwmg6.fsf@intel.com> (raw)
In-Reply-To: <20240827081205.136569-1-arun.r.murthy@intel.com>

On Tue, 27 Aug 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> UHBR20 is not supported by battlemage and the maximum link rate
> supported is UHBR13.5
>
> v2: Replace IS_DGFX with IS_BATTLEMAGE (Jani)
>
> HSD: 16023263677
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>

Also,

Fixes: 98b1c87a5e51 ("drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5")

because that one doesn't DTRT.

BR,
Jani.




> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 789c2f78826d..99a365a945ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -528,6 +528,10 @@ static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	/* The values must be in increasing order */
> +	static const int bmg_rates[] = {
> +		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
> +		810000,	1000000, 1350000,
> +	};
>  	static const int mtl_rates[] = {
>  		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
>  		810000,	1000000, 2000000,
> @@ -558,8 +562,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		    intel_dp->source_rates || intel_dp->num_source_rates);
>  
>  	if (DISPLAY_VER(dev_priv) >= 14) {
> -		source_rates = mtl_rates;
> -		size = ARRAY_SIZE(mtl_rates);
> +		if (IS_BATTLEMAGE(dev_priv)) {
> +			source_rates = bmg_rates;
> +			size = ARRAY_SIZE(bmg_rates);
> +		} else {
> +			source_rates = mtl_rates;
> +			size = ARRAY_SIZE(mtl_rates);
> +		}
>  		max_rate = mtl_max_source_rate(intel_dp);
>  	} else if (DISPLAY_VER(dev_priv) >= 11) {
>  		source_rates = icl_rates;

-- 
Jani Nikula, Intel

  parent reply	other threads:[~2024-08-29 12:19 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-27  8:12 [PATCHv2] drm/i915/display: BMG supports UHBR13.5 Arun R Murthy
2024-08-27 10:03 ` ✗ Fi.CI.BAT: failure for drm/i915/display: BMG supports UHBR13.5 (rev2) Patchwork
2024-08-27 12:54 ` [PATCHv2] drm/i915/display: BMG supports UHBR13.5 Kahola, Mika
2024-08-28  6:45 ` ✓ Fi.CI.BAT: success for drm/i915/display: BMG supports UHBR13.5 (rev3) Patchwork
2024-08-28 10:02 ` [PATCHv2] drm/i915/display: BMG supports UHBR13.5 Govindapillai, Vinod
2024-08-28 11:21   ` Jani Nikula
2024-08-29  7:58 ` ✗ Fi.CI.IGT: failure for drm/i915/display: BMG supports UHBR13.5 (rev3) Patchwork
2024-08-29 12:19 ` Jani Nikula [this message]
2024-09-03  8:08 ` ✓ Fi.CI.BAT: success for drm/i915/display: BMG supports UHBR13.5 (rev4) Patchwork
2024-09-04 11:07 ` ✓ Fi.CI.IGT: " Patchwork

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