* [PATCH 1/2] drm/i915/glk: Split GLK DSI device ready functionality
@ 2017-06-13 7:48 Madhav Chauhan
2017-06-13 7:48 ` [PATCH 2/2] drm/i915/glk: Add cold boot sequence for GLK DSI Madhav Chauhan
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Madhav Chauhan @ 2017-06-13 7:48 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ander.conselvan.de.oliveira, shashidhar.hiremath
This patch divides glk_dsi_device_ready() function into
two part. First part will program LP wake and MIPI DSI mode
to MIPI_CTRL reg using newly defined function glk_dsi_enable_io().
glk_dsi_enable_io() will be called from intel_dsi_pre_enable.
Second part will do remaining device ready activities using
the existing function glk_dsi_device_ready().
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 54030b6..6074014 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -346,12 +346,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
return true;
}
-static void glk_dsi_device_ready(struct intel_encoder *encoder)
+static void glk_dsi_enable_io(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
- u32 tmp, val;
+ u32 tmp;
/* Set the MIPI mode
* If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
@@ -381,6 +381,14 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
GLK_MIPIIO_PORT_POWERED, 20))
DRM_ERROR("MIPIO port is powergated\n");
}
+}
+
+static void glk_dsi_device_ready(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 val;
/* Wait for MIPI PHY status bit to set */
for_each_dsi_port(port, intel_dsi->ports) {
@@ -391,8 +399,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
}
/* Get IO out of reset */
- tmp = I915_READ(MIPI_CTRL(PORT_A));
- I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
+ val = I915_READ(MIPI_CTRL(PORT_A));
+ I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
/* Get IO out of Low power state*/
for_each_dsi_port(port, intel_dsi->ports) {
@@ -427,9 +435,9 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
I915_WRITE(MIPI_DEVICE_READY(port), val);
- tmp = I915_READ(MIPI_CTRL(port));
- tmp &= ~GLK_LP_WAKE;
- I915_WRITE(MIPI_CTRL(port), tmp);
+ val = I915_READ(MIPI_CTRL(port));
+ val &= ~GLK_LP_WAKE;
+ I915_WRITE(MIPI_CTRL(port), val);
}
/* Wait for Stop state */
@@ -811,6 +819,9 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
/* Deassert reset */
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+ if (IS_GEMINILAKE(dev_priv))
+ glk_dsi_enable_io(encoder);
+
/* Put device in ready state (LP-11) */
intel_dsi_device_ready(encoder);
--
1.9.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/i915/glk: Add cold boot sequence for GLK DSI
2017-06-13 7:48 [PATCH 1/2] drm/i915/glk: Split GLK DSI device ready functionality Madhav Chauhan
@ 2017-06-13 7:48 ` Madhav Chauhan
2017-06-13 8:11 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Split GLK DSI device ready functionality Patchwork
2017-06-15 20:51 ` [PATCH 1/2] " Jani Nikula
2 siblings, 0 replies; 4+ messages in thread
From: Madhav Chauhan @ 2017-06-13 7:48 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ander.conselvan.de.oliveira, shashidhar.hiremath
As per BSEPC, if device ready bit is '0' in enable IO sequence
then its a cold boot/reset scenario eg: S3/S4 resume. If cold boot
scenario detected in enable IO, then prepare port immediately.
In normal boot scenario, prepare port after glk_dsi_device_ready().
Without cold boot sequence enabled, features like S3/S4 doesn't work.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 79 ++++++++++++++++++++++++++--------------
1 file changed, 51 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 6074014..3d98f8d5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -346,12 +346,13 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
return true;
}
-static void glk_dsi_enable_io(struct intel_encoder *encoder)
+static bool glk_dsi_enable_io(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
u32 tmp;
+ bool cold_boot = false;
/* Set the MIPI mode
* If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
@@ -370,7 +371,10 @@ static void glk_dsi_enable_io(struct intel_encoder *encoder)
/* Program LP Wake */
for_each_dsi_port(port, intel_dsi->ports) {
tmp = I915_READ(MIPI_CTRL(port));
- tmp |= GLK_LP_WAKE;
+ if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
+ tmp &= ~GLK_LP_WAKE;
+ else
+ tmp |= GLK_LP_WAKE;
I915_WRITE(MIPI_CTRL(port), tmp);
}
@@ -381,6 +385,14 @@ static void glk_dsi_enable_io(struct intel_encoder *encoder)
GLK_MIPIIO_PORT_POWERED, 20))
DRM_ERROR("MIPIO port is powergated\n");
}
+
+ /* Check for cold boot scenario */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
+ DEVICE_READY);
+ }
+
+ return cold_boot;
}
static void glk_dsi_device_ready(struct intel_encoder *encoder)
@@ -410,34 +422,34 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
val |= DEVICE_READY;
I915_WRITE(MIPI_DEVICE_READY(port), val);
usleep_range(10, 15);
- }
-
- /* Enter ULPS */
- val = I915_READ(MIPI_DEVICE_READY(port));
- val &= ~ULPS_STATE_MASK;
- val |= (ULPS_STATE_ENTER | DEVICE_READY);
- I915_WRITE(MIPI_DEVICE_READY(port), val);
+ } else {
+ /* Enter ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_ENTER | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
- /* Wait for ULPS active */
- if (intel_wait_for_register(dev_priv,
+ /* Wait for ULPS active */
+ if (intel_wait_for_register(dev_priv,
MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
- DRM_ERROR("ULPS not active\n");
+ DRM_ERROR("ULPS not active\n");
- /* Exit ULPS */
- val = I915_READ(MIPI_DEVICE_READY(port));
- val &= ~ULPS_STATE_MASK;
- val |= (ULPS_STATE_EXIT | DEVICE_READY);
- I915_WRITE(MIPI_DEVICE_READY(port), val);
+ /* Exit ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_EXIT | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
- /* Enter Normal Mode */
- val = I915_READ(MIPI_DEVICE_READY(port));
- val &= ~ULPS_STATE_MASK;
- val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
- I915_WRITE(MIPI_DEVICE_READY(port), val);
+ /* Enter Normal Mode */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
- val = I915_READ(MIPI_CTRL(port));
- val &= ~GLK_LP_WAKE;
- I915_WRITE(MIPI_CTRL(port), val);
+ val = I915_READ(MIPI_CTRL(port));
+ val &= ~GLK_LP_WAKE;
+ I915_WRITE(MIPI_CTRL(port), val);
+ }
}
/* Wait for Stop state */
@@ -778,6 +790,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
u32 val;
+ bool glk_cold_boot = false;
DRM_DEBUG_KMS("\n");
@@ -808,7 +821,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
I915_WRITE(DSPCLK_GATE_D, val);
}
- intel_dsi_prepare(encoder, pipe_config);
+ if (!IS_GEMINILAKE(dev_priv))
+ intel_dsi_prepare(encoder, pipe_config);
/* Power on, try both CRC pmic gpio and VBT */
if (intel_dsi->gpio_panel)
@@ -819,12 +833,21 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
/* Deassert reset */
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
- if (IS_GEMINILAKE(dev_priv))
- glk_dsi_enable_io(encoder);
+ if (IS_GEMINILAKE(dev_priv)) {
+ glk_cold_boot = glk_dsi_enable_io(encoder);
+ if (glk_cold_boot)
+ /* Prepare port in cold boot(s3/s4) scenario */
+ intel_dsi_prepare(encoder, pipe_config);
+ }
/* Put device in ready state (LP-11) */
intel_dsi_device_ready(encoder);
+ if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
+ /* Prepare port in normal boot scenario */
+ intel_dsi_prepare(encoder, pipe_config);
+
+
/* Send initialization commands in LP mode */
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Split GLK DSI device ready functionality
2017-06-13 7:48 [PATCH 1/2] drm/i915/glk: Split GLK DSI device ready functionality Madhav Chauhan
2017-06-13 7:48 ` [PATCH 2/2] drm/i915/glk: Add cold boot sequence for GLK DSI Madhav Chauhan
@ 2017-06-13 8:11 ` Patchwork
2017-06-15 20:51 ` [PATCH 1/2] " Jani Nikula
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-06-13 8:11 UTC (permalink / raw)
To: Madhav Chauhan; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/glk: Split GLK DSI device ready functionality
URL : https://patchwork.freedesktop.org/series/25700/
State : success
== Summary ==
Series 25700v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25700/revisions/1/mbox/
Test kms_busy:
Subgroup basic-flip-default-b:
fail -> DMESG-WARN (fi-skl-6700hq) fdo#101144
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:442s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:433s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:579s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:510s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:484s
fi-glk-2a total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:592s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:436s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:415s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:496s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:465s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:469s
fi-kbl-7560u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:568s
fi-kbl-r total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time:578s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:477s
fi-skl-6700hq total:278 pass:228 dwarn:2 dfail:0 fail:26 skip:22 time:408s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:468s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:477s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:439s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:531s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:401s
4f89fbd3f94f4ba47f779909a2c7bcd1cfb958ad drm-tip: 2017y-06m-12d-19h-18m-52s UTC integration manifest
0c7eeb3 drm/i915/glk: Add cold boot sequence for GLK DSI
ded0d24 drm/i915/glk: Split GLK DSI device ready functionality
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4938/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/i915/glk: Split GLK DSI device ready functionality
2017-06-13 7:48 [PATCH 1/2] drm/i915/glk: Split GLK DSI device ready functionality Madhav Chauhan
2017-06-13 7:48 ` [PATCH 2/2] drm/i915/glk: Add cold boot sequence for GLK DSI Madhav Chauhan
2017-06-13 8:11 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Split GLK DSI device ready functionality Patchwork
@ 2017-06-15 20:51 ` Jani Nikula
2 siblings, 0 replies; 4+ messages in thread
From: Jani Nikula @ 2017-06-15 20:51 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
Cc: ander.conselvan.de.oliveira, shashidhar.hiremath
On Tue, 13 Jun 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch divides glk_dsi_device_ready() function into
> two part. First part will program LP wake and MIPI DSI mode
> to MIPI_CTRL reg using newly defined function glk_dsi_enable_io().
> glk_dsi_enable_io() will be called from intel_dsi_pre_enable.
> Second part will do remaining device ready activities using
> the existing function glk_dsi_device_ready().
Both pushed to dinq, thanks for the patches.
BR,
Jani.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 25 ++++++++++++++++++-------
> 1 file changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 54030b6..6074014 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -346,12 +346,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> return true;
> }
>
> -static void glk_dsi_device_ready(struct intel_encoder *encoder)
> +static void glk_dsi_enable_io(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> - u32 tmp, val;
> + u32 tmp;
>
> /* Set the MIPI mode
> * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> @@ -381,6 +381,14 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
> GLK_MIPIIO_PORT_POWERED, 20))
> DRM_ERROR("MIPIO port is powergated\n");
> }
> +}
> +
> +static void glk_dsi_device_ready(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 val;
>
> /* Wait for MIPI PHY status bit to set */
> for_each_dsi_port(port, intel_dsi->ports) {
> @@ -391,8 +399,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
> }
>
> /* Get IO out of reset */
> - tmp = I915_READ(MIPI_CTRL(PORT_A));
> - I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
> + val = I915_READ(MIPI_CTRL(PORT_A));
> + I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
>
> /* Get IO out of Low power state*/
> for_each_dsi_port(port, intel_dsi->ports) {
> @@ -427,9 +435,9 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
> val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> I915_WRITE(MIPI_DEVICE_READY(port), val);
>
> - tmp = I915_READ(MIPI_CTRL(port));
> - tmp &= ~GLK_LP_WAKE;
> - I915_WRITE(MIPI_CTRL(port), tmp);
> + val = I915_READ(MIPI_CTRL(port));
> + val &= ~GLK_LP_WAKE;
> + I915_WRITE(MIPI_CTRL(port), val);
> }
>
> /* Wait for Stop state */
> @@ -811,6 +819,9 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> /* Deassert reset */
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
>
> + if (IS_GEMINILAKE(dev_priv))
> + glk_dsi_enable_io(encoder);
> +
> /* Put device in ready state (LP-11) */
> intel_dsi_device_ready(encoder);
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-06-15 20:51 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2017-06-13 7:48 [PATCH 1/2] drm/i915/glk: Split GLK DSI device ready functionality Madhav Chauhan
2017-06-13 7:48 ` [PATCH 2/2] drm/i915/glk: Add cold boot sequence for GLK DSI Madhav Chauhan
2017-06-13 8:11 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Split GLK DSI device ready functionality Patchwork
2017-06-15 20:51 ` [PATCH 1/2] " Jani Nikula
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