[GLK MIPI DSI V5 0/8] GLK MIPI DSI VIDEO MODE PATCHES

[GLK MIPI DSI V5 0/8] GLK MIPI DSI VIDEO MODE PATCHES

[Madhav Chauhan]

The patches in this list enable MIPI DSI video mode
support for GLK platform. Tesed locally.
v2: Renamed bitfields macros as per review comments(Jani)
v3: Code alignment/abstraction as per arch (Jani review comments)
v4: Fix MIPI DSI disable sequence. Review comments(Jani)
v5: Review comments addressed for restructuring code (Jani & Ander)

Deepak M (7):
  drm/i915/glk: Program dphy param reg for GLK
  drm/i915/glk: Program new MIPI DSI PHY registers for GLK
  drm/i915/glk: Add MIPIIO Enable/disable sequence
  drm/i915: Set the Z inversion overlap field
  drm/i915/glk: Add DSI PLL divider range for glk
  drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
  drm/i915/glk: Program txesc clock divider for GLK

Madhav Chauhan (1):
  drm/i915/glk: Validate only DSI PORT A PLL divider

 drivers/gpu/drm/i915/i915_reg.h            |  17 +++
 drivers/gpu/drm/i915/intel_dsi.c           | 231 +++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  31 ++--
 drivers/gpu/drm/i915/intel_dsi_pll.c       | 129 ++++++++++++----
 4 files changed, 353 insertions(+), 55 deletions(-)

-- 
1.9.1

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[GLK MIPI DSI V5 1/8] drm/i915/glk: Program dphy param reg for GLK

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

For GEMINILAKE, dphy param reg values are programmed in terms
of HS byte clock count while for older platforms in terms of
HS ddr clk count.

v2: Added comments to clarify ddr clock count calculation
v3: Use multiplier variable instead of IS_GEMINILAKE()
check everywhere (Jani)

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 31 +++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 8f683b8..d06e7f7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -571,6 +571,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
 	u32 lp_to_hs_switch, hs_to_lp_switch;
 	u32 pclk, computed_ddr;
+	u32 mul;
 	u16 burst_mode_ratio;
 	enum port port;
 
@@ -674,11 +675,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 		break;
 	}
 
-	/*
-	 * ui(s) = 1/f [f in hz]
-	 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
-	 */
-
 	/* in Kbps */
 	ui_num = NS_KHZ_RATIO;
 	ui_den = bitrate;
@@ -692,21 +688,26 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	 */
 	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 
-	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
+	/* DDR clock period = 2 * UI
+	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
+	 * UI(nsec) = 10^6 / bitrate
+	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
+	 * DDR clock count  = ns_value / DDR clock period
 	 *
-	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
-	 * DPHY param register are divided by 2
-	 *
-	 * prepare count
+	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
+	 * HS byte clock count for other platform in HS ddr clock count
 	 */
+	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
 	ths_prepare_ns = max(mipi_config->ths_prepare,
 			     mipi_config->tclk_prepare);
-	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
+
+	/* prepare count */
+	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
 
 	/* exit zero count */
 	exit_zero_cnt = DIV_ROUND_UP(
 				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
-				ui_num * 2
+				ui_num * mul
 				);
 
 	/*
@@ -720,12 +721,12 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	/* clk zero count */
 	clk_zero_cnt = DIV_ROUND_UP(
-			(tclk_prepare_clkzero -	ths_prepare_ns)
-			* ui_den, 2 * ui_num);
+				(tclk_prepare_clkzero -	ths_prepare_ns)
+				* ui_den, ui_num * mul);
 
 	/* trail count */
 	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
-	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
+	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
 
 	if (prepare_cnt > PREPARE_CNT_MAX ||
 		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
-- 
1.9.1

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Re: [GLK MIPI DSI V5 1/8] drm/i915/glk: Program dphy param reg for GLK

[Jani Nikula]

On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> For GEMINILAKE, dphy param reg values are programmed in terms
> of HS byte clock count while for older platforms in terms of
> HS ddr clk count.
>
> v2: Added comments to clarify ddr clock count calculation
> v3: Use multiplier variable instead of IS_GEMINILAKE()
> check everywhere (Jani)
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 31 +++++++++++++++---------------
>  1 file changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 8f683b8..d06e7f7 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -571,6 +571,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>  	u32 lp_to_hs_switch, hs_to_lp_switch;
>  	u32 pclk, computed_ddr;
> +	u32 mul;
>  	u16 burst_mode_ratio;
>  	enum port port;
>  
> @@ -674,11 +675,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  		break;
>  	}
>  
> -	/*
> -	 * ui(s) = 1/f [f in hz]
> -	 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
> -	 */
> -
>  	/* in Kbps */
>  	ui_num = NS_KHZ_RATIO;
>  	ui_den = bitrate;
> @@ -692,21 +688,26 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	 */
>  	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
>  
> -	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
> +	/* DDR clock period = 2 * UI
> +	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> +	 * UI(nsec) = 10^6 / bitrate
> +	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> +	 * DDR clock count  = ns_value / DDR clock period
>  	 *
> -	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
> -	 * DPHY param register are divided by 2
> -	 *
> -	 * prepare count
> +	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
> +	 * HS byte clock count for other platform in HS ddr clock count
>  	 */
> +	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
>  	ths_prepare_ns = max(mipi_config->ths_prepare,
>  			     mipi_config->tclk_prepare);
> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
> +
> +	/* prepare count */
> +	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
>  
>  	/* exit zero count */
>  	exit_zero_cnt = DIV_ROUND_UP(
>  				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
> -				ui_num * 2
> +				ui_num * mul
>  				);
>  
>  	/*
> @@ -720,12 +721,12 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  
>  	/* clk zero count */
>  	clk_zero_cnt = DIV_ROUND_UP(
> -			(tclk_prepare_clkzero -	ths_prepare_ns)
> -			* ui_den, 2 * ui_num);
> +				(tclk_prepare_clkzero -	ths_prepare_ns)
> +				* ui_den, ui_num * mul);
>  
>  	/* trail count */
>  	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
> +	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
>  
>  	if (prepare_cnt > PREPARE_CNT_MAX ||
>  		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||

-- 
Jani Nikula, Intel Open Source Technology Center
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[GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

Program the clk lane and tlpx time count registers
to configure DSI PHY.

v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
v4: Removed "line over 80 character" warning

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
 drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 141a5c1..c09f665 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8636,6 +8636,14 @@ enum {
 #define  LP_BYTECLK_SHIFT				0
 #define  LP_BYTECLK_MASK				(0xffff << 0)
 
+#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
+#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
+
+#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
+#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
+
 /* bits 31:0 */
 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c98234e..03d0999 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1303,6 +1303,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 		 */
 		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 
+		if (IS_GEMINILAKE(dev_priv)) {
+			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
+					intel_dsi->lp_byte_clk);
+			/* Shadow of DPHY reg */
+			I915_WRITE(MIPI_CLK_LANE_TIMING(port),
+					intel_dsi->dphy_reg);
+		}
+
 		/* the bw essential for transmitting 16 long packets containing
 		 * 252 bytes meant for dcs write memory command is programmed in
 		 * this register in terms of byte clocks. based on dsi transfer
-- 
1.9.1

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Re: [GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

[Jani Nikula]

On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Program the clk lane and tlpx time count registers
> to configure DSI PHY.
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Program clk lane timing reg same as dphy param reg.
> v4: Removed "line over 80 character" warning
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
>  drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++
>  2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 141a5c1..c09f665 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8636,6 +8636,14 @@ enum {
>  #define  LP_BYTECLK_SHIFT				0
>  #define  LP_BYTECLK_MASK				(0xffff << 0)
>  
> +#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
> +#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
> +#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
> +
> +#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
> +#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
> +#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
> +
>  /* bits 31:0 */
>  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
>  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index c98234e..03d0999 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1303,6 +1303,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>  		 */
>  		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
>  
> +		if (IS_GEMINILAKE(dev_priv)) {
> +			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
> +					intel_dsi->lp_byte_clk);
> +			/* Shadow of DPHY reg */
> +			I915_WRITE(MIPI_CLK_LANE_TIMING(port),
> +					intel_dsi->dphy_reg);
> +		}
> +
>  		/* the bw essential for transmitting 16 long packets containing
>  		 * 252 bytes meant for dcs write memory command is programmed in
>  		 * this register in terms of byte clocks. based on dsi transfer

-- 
Jani Nikula, Intel Open Source Technology Center
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[GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Jani's Review comment for aligning code to platforms and added
wrapper functions.
v4: Corrected enable/disable seuqence as per BSPEC

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 195 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 03d0999..a72a10f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
+static void glk_dsi_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp, val;
+
+	/* Set the MIPI mode
+	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
+	 * Power ON MIPI IO first and then write into IO reset and LP wake bits
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
+	}
+
+	/* Put the IO into reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+	/* Program LP Wake */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp |= GLK_LP_WAKE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+
+	/* Wait for Pwr ACK */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
+				GLK_MIPIIO_PORT_POWERED, 20))
+			DRM_ERROR("Power ACK not received\n");
+	}
+
+	/* Wait for MIPI PHY status bit to set */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
+				GLK_MIPIIO_PORT_POWERED, 20))
+			DRM_ERROR("PHY is not ON\n");
+	}
+
+	/* Get IO out of reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
+
+	/* Get IO out of Low power state*/
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
+			val = I915_READ(MIPI_DEVICE_READY(port));
+			val &= ~ULPS_STATE_MASK;
+			val |= DEVICE_READY;
+			I915_WRITE(MIPI_DEVICE_READY(port), val);
+			usleep_range(10, 15);
+		}
+
+		/* Enter ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_ENTER | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		/* Wait for ULPS Not active */
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
+				GLK_ULPS_NOT_ACTIVE, 20))
+
+		/* Exit ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_EXIT | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		/* Enter Normal Mode */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~GLK_LP_WAKE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+
+	/* Wait for Stop state */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
+				GLK_DATA_LANE_STOP_STATE, 20))
+			DRM_ERROR("Date lane not in STOP state\n");
+	}
+
+	/* Wait for AFE LATCH */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
+				AFE_LATCHOUT, 20))
+			DRM_ERROR("D-PHY not entering LP-11 state\n");
+	}
+}
+
 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -442,8 +545,10 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_device_ready(encoder);
-	else if (IS_GEN9_LP(dev_priv))
+	else if (IS_BROXTON(dev_priv))
 		bxt_dsi_device_ready(encoder);
+	else if (IS_GEMINILAKE(dev_priv))
+		glk_dsi_device_ready(encoder);
 }
 
 static void intel_dsi_port_enable(struct intel_encoder *encoder)
@@ -649,18 +754,20 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		msleep(2);
 	}
 
-	for_each_dsi_port(port, intel_dsi->ports) {
-		/* Panel commands can be sent when clock is in LP11 */
-		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
+	if (!IS_GEMINILAKE(dev_priv)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			/* Panel commands can be sent when clock is in LP11 */
+			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 
-		intel_dsi_reset_clocks(encoder, port);
-		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+			intel_dsi_reset_clocks(encoder, port);
+			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 
-		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
-		temp &= ~VID_MODE_FORMAT_MASK;
-		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
+			temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
+			temp &= ~VID_MODE_FORMAT_MASK;
+			I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 
-		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+			I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+		}
 	}
 	/* if disable packets are sent before sending shutdown packet then in
 	 * some next enable sequence send turn on packet error is observed */
@@ -670,7 +777,73 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		wait_for_dsi_fifo_empty(intel_dsi, port);
 }
 
-static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 val;
+
+	/* Enter ULPS */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_ENTER | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+	}
+
+	/* Wait for MIPI PHY status bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_PHY_STATUS_PORT_READY, 0, 20))
+			DRM_ERROR("PHY is not turning OFF\n");
+	}
+
+	/* Wait for Pwr ACK bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_MIPIIO_PORT_POWERED, 0, 20))
+			DRM_ERROR("MIPI IO Port is not powergated\n");
+	}
+}
+
+static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+
+	/* Put the IO into reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+	/* Wait for MIPI PHY status bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_PHY_STATUS_PORT_READY, 0, 20))
+			DRM_ERROR("PHY is not turning OFF\n");
+	}
+
+	/* Clear MIPI mode */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~GLK_MIPIIO_ENABLE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+}
+
+static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+	glk_dsi_enter_low_power_mode(encoder);
+	glk_dsi_disable_mipi_io(encoder);
+}
+
+static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -713,6 +886,17 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 	}
 }
 
+static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+	    IS_BROXTON(dev_priv))
+		vlv_dsi_clear_device_ready(encoder);
+	else if (IS_GEMINILAKE(dev_priv))
+		glk_dsi_clear_device_ready(encoder);
+}
+
 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 				   struct intel_crtc_state *pipe_config,
 				   struct drm_connector_state *conn_state)
-- 
1.9.1

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Re: [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Jani Nikula]

On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Jani's Review comment for aligning code to platforms and added
> wrapper functions.
> v4: Corrected enable/disable seuqence as per BSPEC
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
>  1 file changed, 195 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 03d0999..a72a10f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  	return true;
>  }
>  
> +static void glk_dsi_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp, val;
> +
> +	/* Set the MIPI mode
> +	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> +	 * Power ON MIPI IO first and then write into IO reset and LP wake bits
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
> +	}
> +
> +	/* Put the IO into reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
> +	/* Program LP Wake */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp |= GLK_LP_WAKE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +
> +	/* Wait for Pwr ACK */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
> +				GLK_MIPIIO_PORT_POWERED, 20))
> +			DRM_ERROR("Power ACK not received\n");
> +	}
> +
> +	/* Wait for MIPI PHY status bit to set */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
> +				GLK_MIPIIO_PORT_POWERED, 20))
> +			DRM_ERROR("PHY is not ON\n");
> +	}

You have the same wait twice here, with different comments and error
messages.

> +
> +	/* Get IO out of reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
> +
> +	/* Get IO out of Low power state*/
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
> +			val = I915_READ(MIPI_DEVICE_READY(port));
> +			val &= ~ULPS_STATE_MASK;
> +			val |= DEVICE_READY;
> +			I915_WRITE(MIPI_DEVICE_READY(port), val);
> +			usleep_range(10, 15);
> +		}
> +
> +		/* Enter ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		/* Wait for ULPS Not active */
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
> +				GLK_ULPS_NOT_ACTIVE, 20))
> +
> +		/* Exit ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_EXIT | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		/* Enter Normal Mode */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp &= ~GLK_LP_WAKE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +
> +	/* Wait for Stop state */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
> +				GLK_DATA_LANE_STOP_STATE, 20))
> +			DRM_ERROR("Date lane not in STOP state\n");
> +	}
> +
> +	/* Wait for AFE LATCH */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
> +				AFE_LATCHOUT, 20))
> +			DRM_ERROR("D-PHY not entering LP-11 state\n");
> +	}
> +}
> +
>  static void bxt_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -442,8 +545,10 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_dsi_device_ready(encoder);
> -	else if (IS_GEN9_LP(dev_priv))
> +	else if (IS_BROXTON(dev_priv))
>  		bxt_dsi_device_ready(encoder);
> +	else if (IS_GEMINILAKE(dev_priv))
> +		glk_dsi_device_ready(encoder);
>  }
>  
>  static void intel_dsi_port_enable(struct intel_encoder *encoder)
> @@ -649,18 +754,20 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  		msleep(2);
>  	}
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		/* Panel commands can be sent when clock is in LP11 */
> -		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> +	if (!IS_GEMINILAKE(dev_priv)) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			/* Panel commands can be sent when clock is in LP11 */
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>  
> -		intel_dsi_reset_clocks(encoder, port);
> -		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +			intel_dsi_reset_clocks(encoder, port);
> +			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>  
> -		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> -		temp &= ~VID_MODE_FORMAT_MASK;
> -		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> +			temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> +			temp &= ~VID_MODE_FORMAT_MASK;
> +			I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
>  
> -		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +		}
>  	}
>  	/* if disable packets are sent before sending shutdown packet then in
>  	 * some next enable sequence send turn on packet error is observed */
> @@ -670,7 +777,73 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  		wait_for_dsi_fifo_empty(intel_dsi, port);
>  }
>  
> -static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 val;
> +
> +	/* Enter ULPS */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +	}
> +
> +	/* Wait for MIPI PHY status bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_PHY_STATUS_PORT_READY, 0, 20))
> +			DRM_ERROR("PHY is not turning OFF\n");
> +	}
> +
> +	/* Wait for Pwr ACK bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_MIPIIO_PORT_POWERED, 0, 20))
> +			DRM_ERROR("MIPI IO Port is not powergated\n");
> +	}
> +}
> +
> +static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp;
> +
> +	/* Put the IO into reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
> +	/* Wait for MIPI PHY status bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_PHY_STATUS_PORT_READY, 0, 20))
> +			DRM_ERROR("PHY is not turning OFF\n");
> +	}
> +
> +	/* Clear MIPI mode */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp &= ~GLK_MIPIIO_ENABLE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +}
> +
> +static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> +	glk_dsi_enter_low_power_mode(encoder);
> +	glk_dsi_disable_mipi_io(encoder);
> +}
> +
> +static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> @@ -713,6 +886,17 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +	    IS_BROXTON(dev_priv))
> +		vlv_dsi_clear_device_ready(encoder);
> +	else if (IS_GEMINILAKE(dev_priv))
> +		glk_dsi_clear_device_ready(encoder);
> +}
> +
>  static void intel_dsi_post_disable(struct intel_encoder *encoder,
>  				   struct intel_crtc_state *pipe_config,
>  				   struct drm_connector_state *conn_state)

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Thursday, February 16, 2017 8:38 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Saarinen, Jani <jani.saarinen@intel.com>;
> Kamath, Sunil <sunil.kamath@intel.com>; Deepak M
> <m.deepak@intel.com>; Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable
> sequence
> 
> On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > v2: Addressed Jani's Review comments(renamed bit field macros)
> > v3: Jani's Review comment for aligning code to platforms and added
> > wrapper functions.
> > v4: Corrected enable/disable seuqence as per BSPEC
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 206
> > ++++++++++++++++++++++++++++++++++++---
> >  1 file changed, 195 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 03d0999..a72a10f 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct
> intel_encoder *encoder,
> >  	return true;
> >  }
> >
> > +static void glk_dsi_device_ready(struct intel_encoder *encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > +	enum port port;
> > +	u32 tmp, val;
> > +
> > +	/* Set the MIPI mode
> > +	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> > +	 * Power ON MIPI IO first and then write into IO reset and LP wake
> bits
> > +	 */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
> > +	}
> > +
> > +	/* Put the IO into reset */
> > +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> > +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> > +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> > +
> > +	/* Program LP Wake */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		tmp |= GLK_LP_WAKE;
> > +		I915_WRITE(MIPI_CTRL(port), tmp);
> > +	}
> > +
> > +	/* Wait for Pwr ACK */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port),
> GLK_MIPIIO_PORT_POWERED,
> > +				GLK_MIPIIO_PORT_POWERED, 20))
> > +			DRM_ERROR("Power ACK not received\n");
> > +	}
> > +
> > +	/* Wait for MIPI PHY status bit to set */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port),
> GLK_MIPIIO_PORT_POWERED,
> > +				GLK_MIPIIO_PORT_POWERED, 20))
> > +			DRM_ERROR("PHY is not ON\n");
> > +	}
> 
> You have the same wait twice here, with different comments and error
> messages.

Right. Second wait has to be done for PHY STATUS bit. Looks like it got messed up
when I renamed the bit definitions. Will correct it. Thanks for pointing out.

> 
> > +
> > +	/* Get IO out of reset */
> > +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> > +	I915_WRITE(MIPI_CTRL(PORT_A), tmp |
> GLK_MIPIIO_RESET_RELEASED);
> > +
> > +	/* Get IO out of Low power state*/
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (!(I915_READ(MIPI_DEVICE_READY(port)) &
> DEVICE_READY)) {
> > +			val = I915_READ(MIPI_DEVICE_READY(port));
> > +			val &= ~ULPS_STATE_MASK;
> > +			val |= DEVICE_READY;
> > +			I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +			usleep_range(10, 15);
> > +		}
> > +
> > +		/* Enter ULPS */
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > +		/* Wait for ULPS Not active */
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
> > +				GLK_ULPS_NOT_ACTIVE, 20))
> > +
> > +		/* Exit ULPS */
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_EXIT | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > +		/* Enter Normal Mode */
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		tmp &= ~GLK_LP_WAKE;
> > +		I915_WRITE(MIPI_CTRL(port), tmp);
> > +	}
> > +
> > +	/* Wait for Stop state */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port),
> GLK_DATA_LANE_STOP_STATE,
> > +				GLK_DATA_LANE_STOP_STATE, 20))
> > +			DRM_ERROR("Date lane not in STOP state\n");
> > +	}
> > +
> > +	/* Wait for AFE LATCH */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
> > +				AFE_LATCHOUT, 20))
> > +			DRM_ERROR("D-PHY not entering LP-11 state\n");
> > +	}
> > +}
> > +
> >  static void bxt_dsi_device_ready(struct intel_encoder *encoder)  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@
> > -442,8 +545,10 @@ static void intel_dsi_device_ready(struct
> > intel_encoder *encoder)
> >
> >  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  		vlv_dsi_device_ready(encoder);
> > -	else if (IS_GEN9_LP(dev_priv))
> > +	else if (IS_BROXTON(dev_priv))
> >  		bxt_dsi_device_ready(encoder);
> > +	else if (IS_GEMINILAKE(dev_priv))
> > +		glk_dsi_device_ready(encoder);
> >  }
> >
> >  static void intel_dsi_port_enable(struct intel_encoder *encoder) @@
> > -649,18 +754,20 @@ static void intel_dsi_disable(struct intel_encoder
> *encoder)
> >  		msleep(2);
> >  	}
> >
> > -	for_each_dsi_port(port, intel_dsi->ports) {
> > -		/* Panel commands can be sent when clock is in LP11 */
> > -		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> > +	if (!IS_GEMINILAKE(dev_priv)) {
> > +		for_each_dsi_port(port, intel_dsi->ports) {
> > +			/* Panel commands can be sent when clock is in LP11
> */
> > +			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> >
> > -		intel_dsi_reset_clocks(encoder, port);
> > -		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> > +			intel_dsi_reset_clocks(encoder, port);
> > +			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> >
> > -		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> > -		temp &= ~VID_MODE_FORMAT_MASK;
> > -		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> > +			temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> > +			temp &= ~VID_MODE_FORMAT_MASK;
> > +			I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> >
> > -		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> > +			I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> > +		}
> >  	}
> >  	/* if disable packets are sent before sending shutdown packet then in
> >  	 * some next enable sequence send turn on packet error is observed
> > */ @@ -670,7 +777,73 @@ static void intel_dsi_disable(struct
> intel_encoder *encoder)
> >  		wait_for_dsi_fifo_empty(intel_dsi, port);  }
> >
> > -static void intel_dsi_clear_device_ready(struct intel_encoder
> > *encoder)
> > +static void glk_dsi_enter_low_power_mode(struct intel_encoder
> > +*encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > +	enum port port;
> > +	u32 val;
> > +
> > +	/* Enter ULPS */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +	}
> > +
> > +	/* Wait for MIPI PHY status bit to unset */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +					    MIPI_CTRL(port),
> > +					    GLK_PHY_STATUS_PORT_READY, 0,
> 20))
> > +			DRM_ERROR("PHY is not turning OFF\n");
> > +	}
> > +
> > +	/* Wait for Pwr ACK bit to unset */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +					    MIPI_CTRL(port),
> > +					    GLK_MIPIIO_PORT_POWERED, 0,
> 20))
> > +			DRM_ERROR("MIPI IO Port is not powergated\n");
> > +	}
> > +}
> > +
> > +static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > +	enum port port;
> > +	u32 tmp;
> > +
> > +	/* Put the IO into reset */
> > +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> > +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> > +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> > +
> > +	/* Wait for MIPI PHY status bit to unset */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +					    MIPI_CTRL(port),
> > +					    GLK_PHY_STATUS_PORT_READY, 0,
> 20))
> > +			DRM_ERROR("PHY is not turning OFF\n");
> > +	}
> > +
> > +	/* Clear MIPI mode */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		tmp &= ~GLK_MIPIIO_ENABLE;
> > +		I915_WRITE(MIPI_CTRL(port), tmp);
> > +	}
> > +}
> > +
> > +static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
> > +{
> > +	glk_dsi_enter_low_power_mode(encoder);
> > +	glk_dsi_disable_mipi_io(encoder);
> > +}
> > +
> > +static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@
> > -713,6 +886,17 @@ static void intel_dsi_clear_device_ready(struct
> intel_encoder *encoder)
> >  	}
> >  }
> >
> > +static void intel_dsi_clear_device_ready(struct intel_encoder
> > +*encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > +	    IS_BROXTON(dev_priv))
> > +		vlv_dsi_clear_device_ready(encoder);
> > +	else if (IS_GEMINILAKE(dev_priv))
> > +		glk_dsi_clear_device_ready(encoder);
> > +}
> > +
> >  static void intel_dsi_post_disable(struct intel_encoder *encoder,
> >  				   struct intel_crtc_state *pipe_config,
> >  				   struct drm_connector_state *conn_state)
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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[GLK MIPI DSI V5 4/8] drm/i915: Set the Z inversion overlap field

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index a72a10f..ef643c1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -561,12 +561,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 
 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 		u32 temp;
-
-		temp = I915_READ(VLV_CHICKEN_3);
-		temp &= ~PIXEL_OVERLAP_CNT_MASK |
+		if (IS_GEN9_LP(dev_priv)) {
+			for_each_dsi_port(port, intel_dsi->ports) {
+				temp = I915_READ(MIPI_CTRL(port));
+				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
+					intel_dsi->pixel_overlap <<
+					BXT_PIXEL_OVERLAP_CNT_SHIFT;
+				I915_WRITE(MIPI_CTRL(port), temp);
+			}
+		} else {
+			temp = I915_READ(VLV_CHICKEN_3);
+			temp &= ~PIXEL_OVERLAP_CNT_MASK |
 					intel_dsi->pixel_overlap <<
 					PIXEL_OVERLAP_CNT_SHIFT;
-		I915_WRITE(VLV_CHICKEN_3, temp);
+			I915_WRITE(VLV_CHICKEN_3, temp);
+		}
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-- 
1.9.1

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Re: [GLK MIPI DSI V5 4/8] drm/i915: Set the Z inversion overlap field

[Jani Nikula]

On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Dual link Z-inversion overlap field is present
> in MIPI_CTRL register unlike the older platforms,
> hence setting the same in this patch.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Pushed this one patch to dinq. This one is really bxt specific, and
should have been first in the series.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
>  1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index a72a10f..ef643c1 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -561,12 +561,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  
>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>  		u32 temp;
> -
> -		temp = I915_READ(VLV_CHICKEN_3);
> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +		if (IS_GEN9_LP(dev_priv)) {
> +			for_each_dsi_port(port, intel_dsi->ports) {
> +				temp = I915_READ(MIPI_CTRL(port));
> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
> +					intel_dsi->pixel_overlap <<
> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
> +				I915_WRITE(MIPI_CTRL(port), temp);
> +			}
> +		} else {
> +			temp = I915_READ(VLV_CHICKEN_3);
> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
>  					intel_dsi->pixel_overlap <<
>  					PIXEL_OVERLAP_CNT_SHIFT;
> -		I915_WRITE(VLV_CHICKEN_3, temp);
> +			I915_WRITE(VLV_CHICKEN_3, temp);
> +		}
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {

-- 
Jani Nikula, Intel Open Source Technology Center
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[GLK MIPI DSI V5 5/8] drm/i915/glk: Add DSI PLL divider range for glk

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.

v2: Code restructure using min and max ratio variables (Ander)

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  4 ++++
 drivers/gpu/drm/i915/intel_dsi_pll.c | 24 +++++++++++++++++-------
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c09f665..2cd7ff7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8348,10 +8348,12 @@ enum {
 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
 #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
 #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define  BXT_DSIC_16X_BY1		(0 << 10)
 #define  BXT_DSIC_16X_BY2		(1 << 10)
 #define  BXT_DSIC_16X_BY3		(2 << 10)
 #define  BXT_DSIC_16X_BY4		(3 << 10)
 #define  BXT_DSIC_16X_MASK		(3 << 10)
+#define  BXT_DSIA_16X_BY1		(0 << 8)
 #define  BXT_DSIA_16X_BY2		(1 << 8)
 #define  BXT_DSIA_16X_BY3		(2 << 8)
 #define  BXT_DSIA_16X_BY4		(3 << 8)
@@ -8361,6 +8363,8 @@ enum {
 
 #define BXT_DSI_PLL_RATIO_MAX		0x7D
 #define BXT_DSI_PLL_RATIO_MIN		0x22
+#define GLK_DSI_PLL_RATIO_MAX		0x6F
+#define GLK_DSI_PLL_RATIO_MIN		0x22
 #define BXT_DSI_PLL_RATIO_MASK		0xFF
 #define BXT_REF_CLOCK_KHZ		19200
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 61440e5..e6383cb 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -430,11 +430,12 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
 }
 
-static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
+static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
 			       struct intel_crtc_state *config)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	u8 dsi_ratio;
+	u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
 	u32 dsi_clk;
 
 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
@@ -446,11 +447,20 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
 	 * round 'up' the result
 	 */
 	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
-	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
-	    dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+
+	if (IS_BROXTON(dev_priv)) {
+		dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
+		dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
+	} else if (IS_GEMINILAKE(dev_priv)) {
+		dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
+		dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
+	}
+
+	if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
 		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
 		return -ECHRNG;
-	}
+	} else
+		DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
 
 	/*
 	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
@@ -462,7 +472,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
 	/* As per recommendation from hardware team,
 	 * Prog PVD ratio =1 if dsi ratio <= 50
 	 */
-	if (dsi_ratio <= 50)
+	if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
 		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
 
 	return 0;
@@ -522,7 +532,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_compute_dsi_pll(encoder, config);
 	else if (IS_GEN9_LP(dev_priv))
-		return bxt_compute_dsi_pll(encoder, config);
+		return gen9lp_compute_dsi_pll(encoder, config);
 
 	return -ENODEV;
 }
-- 
1.9.1

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Re: [GLK MIPI DSI V5 5/8] drm/i915/glk: Add DSI PLL divider range for glk

[Jani Nikula]

On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> PLL divider range for GLK is different than that of
> BXT, hence adding the GLK range check in this patch.
>
> v2: Code restructure using min and max ratio variables (Ander)
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  4 ++++
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 24 +++++++++++++++++-------
>  2 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c09f665..2cd7ff7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8348,10 +8348,12 @@ enum {
>  #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
>  #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
>  #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define  BXT_DSIC_16X_BY1		(0 << 10)
>  #define  BXT_DSIC_16X_BY2		(1 << 10)
>  #define  BXT_DSIC_16X_BY3		(2 << 10)
>  #define  BXT_DSIC_16X_BY4		(3 << 10)
>  #define  BXT_DSIC_16X_MASK		(3 << 10)
> +#define  BXT_DSIA_16X_BY1		(0 << 8)
>  #define  BXT_DSIA_16X_BY2		(1 << 8)
>  #define  BXT_DSIA_16X_BY3		(2 << 8)
>  #define  BXT_DSIA_16X_BY4		(3 << 8)
> @@ -8361,6 +8363,8 @@ enum {
>  
>  #define BXT_DSI_PLL_RATIO_MAX		0x7D
>  #define BXT_DSI_PLL_RATIO_MIN		0x22
> +#define GLK_DSI_PLL_RATIO_MAX		0x6F
> +#define GLK_DSI_PLL_RATIO_MIN		0x22
>  #define BXT_DSI_PLL_RATIO_MASK		0xFF
>  #define BXT_REF_CLOCK_KHZ		19200
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 61440e5..e6383cb 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -430,11 +430,12 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
>  	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>  }
>  
> -static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
> +static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
>  			       struct intel_crtc_state *config)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	u8 dsi_ratio;
> +	u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
>  	u32 dsi_clk;
>  
>  	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> @@ -446,11 +447,20 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
>  	 * round 'up' the result
>  	 */
>  	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
> -	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> -	    dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> +
> +	if (IS_BROXTON(dev_priv)) {
> +		dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
> +		dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
> +	} else if (IS_GEMINILAKE(dev_priv)) {

This else if causes

 drivers/gpu/drm/i915/intel_dsi_pll.c: In function ‘intel_compute_dsi_pll’:
 drivers/gpu/drm/i915/intel_dsi_pll.c:513:45: error: ‘dsi_ratio_max’ may be
 used uninitialized in this function [-Werror=maybe-uninitialized]
   if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
					      ^
 drivers/gpu/drm/i915/intel_dsi_pll.c:492:31: note: ‘dsi_ratio_max’ was
 declared here
   u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
				^

And things like this in our driver generally beg the question, what
*other* platforms than the mentioned ones could run this code.

Just change that to an else.

BR,
Jani.


> +		dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
> +		dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
> +	}
> +
> +	if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
>  		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
>  		return -ECHRNG;
> -	}
> +	} else
> +		DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
>  
>  	/*
>  	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
> @@ -462,7 +472,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
>  	/* As per recommendation from hardware team,
>  	 * Prog PVD ratio =1 if dsi ratio <= 50
>  	 */
> -	if (dsi_ratio <= 50)
> +	if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
>  		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
>  
>  	return 0;
> @@ -522,7 +532,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_compute_dsi_pll(encoder, config);
>  	else if (IS_GEN9_LP(dev_priv))
> -		return bxt_compute_dsi_pll(encoder, config);
> +		return gen9lp_compute_dsi_pll(encoder, config);
>  
>  	return -ENODEV;
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
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[GLK MIPI DSI V5 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

Register MIPI_CLOCK_CTRL is applicable only
for BXT platform. Future platform have other
registers to program the escape clock dividers.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index e6383cb..aadf7de 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -493,8 +493,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
 	POSTING_READ(BXT_DSI_PLL_CTL);
 
 	/* Program TX, RX, Dphy clocks */
-	for_each_dsi_port(port, intel_dsi->ports)
-		bxt_dsi_program_clocks(encoder->base.dev, port, config);
+	if (IS_BROXTON(dev_priv)) {
+		for_each_dsi_port(port, intel_dsi->ports)
+			bxt_dsi_program_clocks(encoder->base.dev, port, config);
+	}
 
 	/* Enable DSI PLL */
 	val = I915_READ(BXT_DSI_PLL_ENABLE);
@@ -558,19 +560,22 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
 		bxt_disable_dsi_pll(encoder);
 }
 
-static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
+				    enum port port)
 {
 	u32 tmp;
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	/* Clear old configurations */
-	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
-	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
-	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
-	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
-	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
-	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+	if (IS_BROXTON(dev_priv)) {
+		tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+		tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+		tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
+		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
+		I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+	}
 	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 }
 
@@ -579,7 +584,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (IS_GEN9_LP(dev_priv))
-		bxt_dsi_reset_clocks(encoder, port);
+		gen9lp_dsi_reset_clocks(encoder, port);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_reset_clocks(encoder, port);
 }
-- 
1.9.1

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Re: [GLK MIPI DSI V5 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT

[Jani Nikula]

On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Register MIPI_CLOCK_CTRL is applicable only
> for BXT platform. Future platform have other
> registers to program the escape clock dividers.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++++++++++++++----------
>  1 file changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index e6383cb..aadf7de 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -493,8 +493,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
>  	POSTING_READ(BXT_DSI_PLL_CTL);
>  
>  	/* Program TX, RX, Dphy clocks */
> -	for_each_dsi_port(port, intel_dsi->ports)
> -		bxt_dsi_program_clocks(encoder->base.dev, port, config);
> +	if (IS_BROXTON(dev_priv)) {
> +		for_each_dsi_port(port, intel_dsi->ports)
> +			bxt_dsi_program_clocks(encoder->base.dev, port, config);
> +	}
>  
>  	/* Enable DSI PLL */
>  	val = I915_READ(BXT_DSI_PLL_ENABLE);
> @@ -558,19 +560,22 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>  		bxt_disable_dsi_pll(encoder);
>  }
>  
> -static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
> +				    enum port port)
>  {
>  	u32 tmp;
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
>  	/* Clear old configurations */
> -	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> -	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> -	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
> -	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> -	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
> -	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> +	if (IS_BROXTON(dev_priv)) {
> +		tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> +		tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> +		tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
> +		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> +		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
> +		I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> +	}
>  	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>  }
>  
> @@ -579,7 +584,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
>  	if (IS_GEN9_LP(dev_priv))
> -		bxt_dsi_reset_clocks(encoder, port);
> +		gen9lp_dsi_reset_clocks(encoder, port);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_dsi_reset_clocks(encoder, port);
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
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[GLK MIPI DSI V5 7/8] drm/i915/glk: Program txesc clock divider for GLK

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

v2: Addressed Jani's Review comments(renamed bit field macros)

Txesc clock divider is calculated and programmed
for geminilake platform.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  5 +++
 drivers/gpu/drm/i915/intel_dsi_pll.c | 61 ++++++++++++++++++++++++++++++++++--
 2 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2cd7ff7..b4c979d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8262,6 +8262,11 @@ enum {
 #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
 
+#define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
+#define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
+#define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
+#define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
+
 /* BXT MIPI clock controls */
 #define BXT_MAX_VAR_OUTPUT_KHZ			39500
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index aadf7de..a7f8e0f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -372,6 +372,53 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 			ESCAPE_CLOCK_DIVIDER_SHIFT);
 }
 
+static void glk_dsi_program_esc_clock(struct drm_device *dev,
+				   const struct intel_crtc_state *config)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	u32 dsi_rate = 0;
+	u32 pll_ratio = 0;
+	u32 ddr_clk = 0;
+	u32 div1_value = 0;
+	u32 div2_value = 0;
+	u32 txesc1_div = 0;
+	u32 txesc2_div = 0;
+
+	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
+
+	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+	ddr_clk = dsi_rate / 2;
+
+	/* Variable divider value */
+	div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
+
+	/* Calculate TXESC1 divider */
+	if (div1_value <= 10)
+		txesc1_div = div1_value;
+	else if ((div1_value > 10) && (div1_value <= 20))
+		txesc1_div = DIV_ROUND_UP(div1_value, 2);
+	else if ((div1_value > 20) && (div1_value <= 30))
+		txesc1_div = DIV_ROUND_UP(div1_value, 4);
+	else if ((div1_value > 30) && (div1_value <= 40))
+		txesc1_div = DIV_ROUND_UP(div1_value, 6);
+	else if ((div1_value > 40) && (div1_value <= 50))
+		txesc1_div = DIV_ROUND_UP(div1_value, 8);
+	else
+		txesc1_div = 10;
+
+	/* Calculate TXESC2 divider */
+	div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
+
+	if (div2_value < 10)
+		txesc2_div = div2_value;
+	else
+		txesc2_div = 10;
+
+	I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
+	I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
+}
+
 /* Program BXT Mipi clocks and dividers */
 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 				   const struct intel_crtc_state *config)
@@ -478,7 +525,7 @@ static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
 	return 0;
 }
 
-static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
+static void gen9lp_enable_dsi_pll(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -496,6 +543,8 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
 	if (IS_BROXTON(dev_priv)) {
 		for_each_dsi_port(port, intel_dsi->ports)
 			bxt_dsi_program_clocks(encoder->base.dev, port, config);
+	} else {
+		glk_dsi_program_esc_clock(encoder->base.dev, config);
 	}
 
 	/* Enable DSI PLL */
@@ -547,7 +596,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_enable_dsi_pll(encoder, config);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_enable_dsi_pll(encoder, config);
+		gen9lp_enable_dsi_pll(encoder, config);
 }
 
 void intel_disable_dsi_pll(struct intel_encoder *encoder)
@@ -575,6 +624,14 @@ static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
 		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
 		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
 		I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+	} else {
+		tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
+		tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
+		I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
+
+		tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
+		tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
+		I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
 	}
 	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 }
-- 
1.9.1

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[GLK MIPI DSI V5 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider

[Madhav Chauhan]

As per BSPEC, GLK supports MIPI DSI 8X clk only on PORT A.
Therefore only for PORT A PLL divider value should be validated.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index a7f8e0f..aa14d96 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -206,17 +206,24 @@ static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
 		return false;
 
 	/*
-	 * Both dividers must be programmed with valid values even if only one
-	 * of the PLL is used, see BSpec/Broxton Clocks. Check this here for
+	 * Dividers must be programmed with valid values. As per BSEPC, for
+	 * GEMINLAKE only PORT A divider values are checked while for BXT
+	 * both divider values are validated. Check this here for
 	 * paranoia, since BIOS is known to misconfigure PLLs in this way at
 	 * times, and since accessing DSI registers with invalid dividers
 	 * causes a system hang.
 	 */
 	val = I915_READ(BXT_DSI_PLL_CTL);
-	if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
-		DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",
-				 val);
-		enabled = false;
+	if (IS_GEMINILAKE(dev_priv)) {
+		if (!(val & BXT_DSIA_16X_MASK)) {
+			DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
+			enabled = false;
+		}
+	} else {
+		if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
+			DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
+			enabled = false;
+		}
 	}
 
 	return enabled;
-- 
1.9.1

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✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev5)

[Patchwork]

== Series Details ==

Series: GLK MIPI DSI VIDEO MODE PATCHES (rev5)
URL   : https://patchwork.freedesktop.org/series/16542/
State : failure

== Summary ==

  CC [M]  drivers/gpu/drm/i915/gvt/trace_points.o
  CC [M]  drivers/gpu/drm/i915/gvt/vgpu.o
  CC [M]  drivers/gpu/drm/i915/gvt/interrupt.o
  CC [M]  drivers/gpu/drm/i915/gvt/cfg_space.o
  CC [M]  drivers/gpu/drm/i915/gvt/gtt.o
  CC [M]  drivers/gpu/drm/i915/gvt/mmio.o
  CC [M]  drivers/gpu/drm/i915/gvt/opregion.o
  CC [M]  drivers/gpu/drm/i915/gvt/display.o
  CC [M]  drivers/gpu/drm/i915/gvt/edid.o
  CC [M]  drivers/gpu/drm/i915/gvt/execlist.o
  CC [M]  drivers/gpu/drm/i915/gvt/scheduler.o
  CC [M]  drivers/gpu/drm/i915/gvt/render.o
  CC [M]  drivers/gpu/drm/i915/gvt/sched_policy.o
  CC [M]  drivers/gpu/drm/i915/gvt/cmd_parser.o
  LD      drivers/md/dm-mod.o
  CC [M]  drivers/gpu/drm/i915/intel_lpe_audio.o
  LD      drivers/spi/built-in.o
  LD      drivers/acpi/acpica/built-in.o
  LD      drivers/tty/serial/8250/8250.o
  LD [M]  drivers/misc/mei/mei-me.o
  LD      drivers/misc/built-in.o
  LD      drivers/acpi/built-in.o
  LD      drivers/iommu/built-in.o
  LD      drivers/usb/gadget/libcomposite.o
  LD      net/xfrm/built-in.o
  LD      drivers/pci/pcie/aer/aerdriver.o
  LD      drivers/pci/pcie/aer/built-in.o
  LD      drivers/pci/pcie/built-in.o
  LD [M]  drivers/gpu/drm/vgem/vgem.o
  LD [M]  drivers/net/ethernet/broadcom/genet/genet.o
  LD [M]  drivers/net/ethernet/intel/igbvf/igbvf.o
  LD      drivers/pci/built-in.o
  LD      drivers/usb/gadget/udc/udc-core.o
  LD      drivers/scsi/scsi_mod.o
  LD      drivers/usb/gadget/udc/built-in.o
  LD      drivers/video/fbdev/core/fb.o
  LD      drivers/usb/gadget/built-in.o
  LD      drivers/video/fbdev/core/built-in.o
  LD      net/ipv6/ipv6.o
  LD      drivers/tty/serial/8250/8250_base.o
  LD      drivers/video/fbdev/built-in.o
  LD      drivers/tty/serial/8250/built-in.o
  LD      net/ipv6/built-in.o
drivers/gpu/drm/i915/intel_dsi_pll.c: In function ‘intel_compute_dsi_pll’:
drivers/gpu/drm/i915/intel_dsi_pll.c:513:45: error: ‘dsi_ratio_max’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
  if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
                                             ^
drivers/gpu/drm/i915/intel_dsi_pll.c:492:31: note: ‘dsi_ratio_max’ was declared here
  u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
                               ^
  LD      drivers/tty/serial/built-in.o
  LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
cc1: all warnings being treated as errors
scripts/Makefile.build:294: recipe for target 'drivers/gpu/drm/i915/intel_dsi_pll.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_dsi_pll.o] Error 1
make[4]: *** Waiting for unfinished jobs....
  LD      drivers/scsi/sd_mod.o
  LD      drivers/scsi/built-in.o
  LD [M]  sound/pci/hda/snd-hda-codec-generic.o
  LD      drivers/gpu/drm/drm.o
  LD      sound/pci/built-in.o
  LD      fs/btrfs/btrfs.o
  AR      lib/lib.a
  EXPORTS lib/lib-ksyms.o
  LD      drivers/usb/core/usbcore.o
  LD      sound/built-in.o
  LD      lib/built-in.o
  LD      drivers/video/console/built-in.o
  LD      drivers/usb/core/built-in.o
  LD      drivers/video/built-in.o
  LD      fs/btrfs/built-in.o
  LD      net/ipv4/built-in.o
  LD      drivers/tty/vt/built-in.o
  LD      drivers/tty/built-in.o
  LD [M]  drivers/net/ethernet/intel/igb/igb.o
  CC      arch/x86/kernel/cpu/capflags.o
  LD      arch/x86/kernel/cpu/built-in.o
  LD      arch/x86/kernel/built-in.o
  LD      drivers/md/md-mod.o
  LD      drivers/md/built-in.o
  LD      drivers/usb/host/xhci-hcd.o
  LD      arch/x86/built-in.o
  LD      drivers/usb/host/built-in.o
  LD      drivers/usb/built-in.o
  LD      fs/ext4/ext4.o
  LD      fs/ext4/built-in.o
  LD      fs/built-in.o
  LD      net/core/built-in.o
  LD      net/built-in.o
  LD [M]  drivers/net/ethernet/intel/e1000e/e1000e.o
  LD      drivers/net/ethernet/built-in.o
  LD      drivers/net/built-in.o
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:988: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev5)

[Jani Nikula]

On Tue, 14 Feb 2017, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> drivers/gpu/drm/i915/intel_dsi_pll.c: In function ‘intel_compute_dsi_pll’:
> drivers/gpu/drm/i915/intel_dsi_pll.c:513:45: error: ‘dsi_ratio_max’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
>   if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
>                                              ^
> drivers/gpu/drm/i915/intel_dsi_pll.c:492:31: note: ‘dsi_ratio_max’ was declared here
>   u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
>                                ^
>   LD      drivers/tty/serial/built-in.o
>   LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
> cc1: all warnings being treated as errors
> scripts/Makefile.build:294: recipe for target 'drivers/gpu/drm/i915/intel_dsi_pll.o' failed
> make[4]: *** [drivers/gpu/drm/i915/intel_dsi_pll.o] Error 1
> make[4]: *** Waiting for unfinished jobs....

The series didn't get tested because of this. Please update the series
and repost, and do remember to add the Reviewed-by tags to the patches
I've reviewed so far.

Thanks,
Jani.



-- 
Jani Nikula, Intel Open Source Technology Center
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Re: ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev5)

[Chauhan, Madhav]

> -----Original Message-----
> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
> Sent: Thursday, February 16, 2017 8:49 PM
> To: Patchwork <patchwork@emeril.freedesktop.org>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE
> PATCHES (rev5)
> 
> On Tue, 14 Feb 2017, Patchwork <patchwork@emeril.freedesktop.org>
> wrote:
> > drivers/gpu/drm/i915/intel_dsi_pll.c: In function ‘intel_compute_dsi_pll’:
> > drivers/gpu/drm/i915/intel_dsi_pll.c:513:45: error: ‘dsi_ratio_max’ may be
> used uninitialized in this function [-Werror=maybe-uninitialized]
> >   if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
> >                                              ^
> > drivers/gpu/drm/i915/intel_dsi_pll.c:492:31: note: ‘dsi_ratio_max’ was
> declared here
> >   u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
> >                                ^
> >   LD      drivers/tty/serial/built-in.o
> >   LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
> > cc1: all warnings being treated as errors
> > scripts/Makefile.build:294: recipe for target
> > 'drivers/gpu/drm/i915/intel_dsi_pll.o' failed
> > make[4]: *** [drivers/gpu/drm/i915/intel_dsi_pll.o] Error 1
> > make[4]: *** Waiting for unfinished jobs....
> 
> The series didn't get tested because of this. Please update the series and
> repost, and do remember to add the Reviewed-by tags to the patches I've
> reviewed so far.

Agree. Surprised to see why I didn’t get this error during compilation in my local environment. Used x86_64_defconfig. Any idea ??

> 
> Thanks,
> Jani.
> 
> 
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev5)

[Jani Nikula]

On Thu, 16 Feb 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>> Sent: Thursday, February 16, 2017 8:49 PM
>> To: Patchwork <patchwork@emeril.freedesktop.org>; Chauhan, Madhav
>> <madhav.chauhan@intel.com>
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE
>> PATCHES (rev5)
>> 
>> On Tue, 14 Feb 2017, Patchwork <patchwork@emeril.freedesktop.org>
>> wrote:
>> > drivers/gpu/drm/i915/intel_dsi_pll.c: In function ‘intel_compute_dsi_pll’:
>> > drivers/gpu/drm/i915/intel_dsi_pll.c:513:45: error: ‘dsi_ratio_max’ may be
>> used uninitialized in this function [-Werror=maybe-uninitialized]
>> >   if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
>> >                                              ^
>> > drivers/gpu/drm/i915/intel_dsi_pll.c:492:31: note: ‘dsi_ratio_max’ was
>> declared here
>> >   u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
>> >                                ^
>> >   LD      drivers/tty/serial/built-in.o
>> >   LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
>> > cc1: all warnings being treated as errors
>> > scripts/Makefile.build:294: recipe for target
>> > 'drivers/gpu/drm/i915/intel_dsi_pll.o' failed
>> > make[4]: *** [drivers/gpu/drm/i915/intel_dsi_pll.o] Error 1
>> > make[4]: *** Waiting for unfinished jobs....
>> 
>> The series didn't get tested because of this. Please update the series and
>> repost, and do remember to add the Reviewed-by tags to the patches I've
>> reviewed so far.
>
> Agree. Surprised to see why I didn’t get this error during compilation
> in my local environment. Used x86_64_defconfig. Any idea ??

The CI usees DRM_I915_WERROR=y, among other debug config options.

BR,
Jani.


>
>> 
>> Thanks,
>> Jani.
>> 
>> 
>> 
>> --
>> Jani Nikula, Intel Open Source Technology Center

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev5)

[Chauhan, Madhav]

> -----Original Message-----
> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
> Sent: Thursday, February 16, 2017 11:45 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; Patchwork
> <patchwork@emeril.freedesktop.org>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE
> PATCHES (rev5)
> 
> On Thu, 16 Feb 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com>
> wrote:
> >> -----Original Message-----
> >> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
> >> Sent: Thursday, February 16, 2017 8:49 PM
> >> To: Patchwork <patchwork@emeril.freedesktop.org>; Chauhan, Madhav
> >> <madhav.chauhan@intel.com>
> >> Cc: intel-gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO
> >> MODE PATCHES (rev5)
> >>
> >> On Tue, 14 Feb 2017, Patchwork <patchwork@emeril.freedesktop.org>
> >> wrote:
> >> > drivers/gpu/drm/i915/intel_dsi_pll.c: In function
> ‘intel_compute_dsi_pll’:
> >> > drivers/gpu/drm/i915/intel_dsi_pll.c:513:45: error: ‘dsi_ratio_max’
> >> > may be
> >> used uninitialized in this function [-Werror=maybe-uninitialized]
> >> >   if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
> >> >                                              ^
> >> > drivers/gpu/drm/i915/intel_dsi_pll.c:492:31: note: ‘dsi_ratio_max’
> >> > was
> >> declared here
> >> >   u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
> >> >                                ^
> >> >   LD      drivers/tty/serial/built-in.o
> >> >   LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
> >> > cc1: all warnings being treated as errors
> >> > scripts/Makefile.build:294: recipe for target
> >> > 'drivers/gpu/drm/i915/intel_dsi_pll.o' failed
> >> > make[4]: *** [drivers/gpu/drm/i915/intel_dsi_pll.o] Error 1
> >> > make[4]: *** Waiting for unfinished jobs....
> >>
> >> The series didn't get tested because of this. Please update the
> >> series and repost, and do remember to add the Reviewed-by tags to the
> >> patches I've reviewed so far.
> >
> > Agree. Surprised to see why I didn’t get this error during compilation
> > in my local environment. Used x86_64_defconfig. Any idea ??
> 
> The CI usees DRM_I915_WERROR=y, among other debug config options.

I had enabled that option while testing but no warning/error. Looks like we need to
add  "maybe-uninitialized" to Werror lists or something else.

> 
> BR,
> Jani.
> 
> 
> >
> >>
> >> Thanks,
> >> Jani.
> >>
> >>
> >>
> >> --
> >> Jani Nikula, Intel Open Source Technology Center
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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