From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/8] drm/i915/execlists: Move clearing submission count from reset to init
Date: Mon, 03 Oct 2016 16:07:50 +0300 [thread overview]
Message-ID: <87lgy54m3d.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20161003125246.17686-3-chris@chris-wilson.co.uk>
Chris Wilson <chris@chris-wilson.co.uk> writes:
> After a GPU reset, we want to replay our queue of requests. However, the
> GPU reset clobbered the state and we only fixup the state for the
> guitly
s/guitly/guilty.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> request - and engines deemed innocent we try to leave untouched so that
> we recover as completely as possible. However, we need to clear the sw
> tracking of the ELSP ports even for innocent requests, so move the clear
> to the common path of init_hw (from reset_hw).
>
> Reported-by: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0ea992ba2723..936f6f63f626 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1242,8 +1242,12 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
>
> intel_engine_init_hangcheck(engine);
>
> - if (!execlists_elsp_idle(engine))
> + /* After a GPU reset, we may have requests to replay */
> + if (!execlists_elsp_idle(engine)) {
> + engine->execlist_port[0].count = 0;
> + engine->execlist_port[1].count = 0;
> execlists_submit_ports(engine);
> + }
>
> return 0;
> }
> @@ -1318,10 +1322,7 @@ static void reset_common_ring(struct intel_engine_cs *engine,
> memset(&port[1], 0, sizeof(port[1]));
> }
>
> - /* CS is stopped, and we will resubmit both ports on resume */
> GEM_BUG_ON(request->ctx != port[0].request->ctx);
> - port[0].count = 0;
> - port[1].count = 0;
>
> /* Reset WaIdleLiteRestore:bdw,skl as well */
> request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
> --
> 2.9.3
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next prev parent reply other threads:[~2016-10-03 13:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-03 12:52 [PATCH 1/8] drm/i915: Share the computation of ring size for RING_CTL register Chris Wilson
2016-10-03 12:52 ` [PATCH 2/8] drm/i915/execlists: Reinitialise context image after GPU hang Chris Wilson
2016-10-03 12:52 ` [PATCH 3/8] drm/i915/execlists: Move clearing submission count from reset to init Chris Wilson
2016-10-03 13:07 ` Mika Kuoppala [this message]
2016-10-03 12:52 ` [PATCH 4/8] drm/i915: Disable irqs across GPU reset Chris Wilson
2016-10-03 13:09 ` Mika Kuoppala
2016-10-03 12:52 ` [PATCH 5/8] drm/i915: Double check hangcheck.seqno after reset Chris Wilson
2016-10-03 13:14 ` Mika Kuoppala
2016-10-03 14:01 ` Chris Wilson
2016-10-03 12:52 ` [PATCH 6/8] drm/i915: Show bounds of active request in the ring on GPU hang Chris Wilson
2016-10-04 11:56 ` Mika Kuoppala
2016-10-03 12:52 ` [PATCH 7/8] drm/i915: Show RING registers through debugfs Chris Wilson
2016-10-04 12:35 ` Mika Kuoppala
2016-10-04 13:11 ` Chris Wilson
2016-10-03 12:52 ` [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info Chris Wilson
2016-10-04 12:41 ` Mika Kuoppala
2016-10-04 13:07 ` Chris Wilson
2016-10-04 13:22 ` Mika Kuoppala
2016-10-03 13:00 ` [PATCH 1/8] drm/i915: Share the computation of ring size for RING_CTL register Chris Wilson
2016-10-04 12:51 ` Mika Kuoppala
2016-10-03 13:01 ` Mika Kuoppala
2016-10-03 14:49 ` ✗ Fi.CI.BAT: warning for series starting with [1/8] " Patchwork
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