Re: [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers

Francisco Jerez
2016-03-08T22:07:25Z

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Jordan Justen <jordan.l.justen@intel.com> writes:

> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index e1608da..f8381be 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
> * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> * 5. GPGPU dispatch compute indirect registers.
> + * 6. TIMESTAMP register and Haswell CS GPR registers
> */
> - return 5;
> + return 6;
> }
> --
> 2.7.0
>
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