* [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
@ 2014-10-29 7:02 Dave Airlie
2014-10-29 7:40 ` [Intel-gfx] " Daniel Vetter
2014-10-29 8:15 ` Ville Syrjälä
0 siblings, 2 replies; 8+ messages in thread
From: Dave Airlie @ 2014-10-29 7:02 UTC (permalink / raw)
To: dri-devel; +Cc: intel-gfx
From: Dave Airlie <airlied@redhat.com>
Ivybridge + 30" monitor prints a drm error on every modeset, since
IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f6a3fdd..87cfb92 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
void
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
+ struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
+ struct drm_device *dev = encoder->dev;
bool channel_eq = false;
int tries, cr_tries;
uint32_t DP = intel_dp->DP;
uint32_t training_pattern = DP_TRAINING_PATTERN_2;
/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
- if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+ if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
training_pattern = DP_TRAINING_PATTERN_3;
/* channel equalization */
--
1.9.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
2014-10-29 7:02 [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell Dave Airlie
@ 2014-10-29 7:40 ` Daniel Vetter
2014-10-29 8:15 ` Ville Syrjälä
1 sibling, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2014-10-29 7:40 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx, dri-devel
On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> Ivybridge + 30" monitor prints a drm error on every modeset, since
> IVB doesn't support DP3 we should even bother trying to use it.
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
> Signed-off-by: Dave Airlie <airlied@redhat.com>
This regression has been introduced in
commit 06ea66b6bb445043dc25a9626254d5c130093199
Author: Todd Previte <tprevite@gmail.com>
Date: Mon Jan 20 10:19:39 2014 -0700
drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices
Cc: Todd Previte <tprevite@gmail.com>
Cc: stable@vger.kernel.org
Jani, can you please pick this one up?
-Daniel
> ---
> drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f6a3fdd..87cfb92 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> void
> intel_dp_complete_link_train(struct intel_dp *intel_dp)
> {
> + struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> + struct drm_device *dev = encoder->dev;
> bool channel_eq = false;
> int tries, cr_tries;
> uint32_t DP = intel_dp->DP;
> uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>
> /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> - if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> + if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
> training_pattern = DP_TRAINING_PATTERN_3;
>
> /* channel equalization */
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
2014-10-29 7:02 [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell Dave Airlie
2014-10-29 7:40 ` [Intel-gfx] " Daniel Vetter
@ 2014-10-29 8:15 ` Ville Syrjälä
2014-10-29 8:22 ` [Intel-gfx] " Ville Syrjälä
2014-10-29 8:23 ` Jani Nikula
1 sibling, 2 replies; 8+ messages in thread
From: Ville Syrjälä @ 2014-10-29 8:15 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx, dri-devel
On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> Ivybridge + 30" monitor prints a drm error on every modeset, since
> IVB doesn't support DP3 we should even bother trying to use it.
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f6a3fdd..87cfb92 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> void
> intel_dp_complete_link_train(struct intel_dp *intel_dp)
> {
> + struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> + struct drm_device *dev = encoder->dev;
> bool channel_eq = false;
> int tries, cr_tries;
> uint32_t DP = intel_dp->DP;
> uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>
> /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> - if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> + if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
CHV has pattern 3.
> training_pattern = DP_TRAINING_PATTERN_3;
>
> /* channel equalization */
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
2014-10-29 8:15 ` Ville Syrjälä
@ 2014-10-29 8:22 ` Ville Syrjälä
2014-10-29 8:23 ` Jani Nikula
1 sibling, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2014-10-29 8:22 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx, dri-devel
On Wed, Oct 29, 2014 at 10:15:01AM +0200, Ville Syrjälä wrote:
> On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> > From: Dave Airlie <airlied@redhat.com>
> >
> > Ivybridge + 30" monitor prints a drm error on every modeset, since
> > IVB doesn't support DP3 we should even bother trying to use it.
> >
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
> > Signed-off-by: Dave Airlie <airlied@redhat.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f6a3fdd..87cfb92 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> > void
> > intel_dp_complete_link_train(struct intel_dp *intel_dp)
> > {
> > + struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> > + struct drm_device *dev = encoder->dev;
> > bool channel_eq = false;
> > int tries, cr_tries;
> > uint32_t DP = intel_dp->DP;
> > uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> >
> > /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> > - if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> > + if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
>
> CHV has pattern 3.
Also what's that '!' doing there?
>
> > training_pattern = DP_TRAINING_PATTERN_3;
> >
> > /* channel equalization */
> > --
> > 1.9.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
2014-10-29 8:15 ` Ville Syrjälä
2014-10-29 8:22 ` [Intel-gfx] " Ville Syrjälä
@ 2014-10-29 8:23 ` Jani Nikula
2014-10-29 8:40 ` [Intel-gfx] " Ville Syrjälä
1 sibling, 1 reply; 8+ messages in thread
From: Jani Nikula @ 2014-10-29 8:23 UTC (permalink / raw)
To: Ville Syrjälä, Dave Airlie; +Cc: intel-gfx, dri-devel
On Wed, 29 Oct 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
>> From: Dave Airlie <airlied@redhat.com>
>>
>> Ivybridge + 30" monitor prints a drm error on every modeset, since
>> IVB doesn't support DP3 we should even bother trying to use it.
>>
>> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
>> Signed-off-by: Dave Airlie <airlied@redhat.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index f6a3fdd..87cfb92 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>> void
>> intel_dp_complete_link_train(struct intel_dp *intel_dp)
>> {
>> + struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
>> + struct drm_device *dev = encoder->dev;
>> bool channel_eq = false;
>> int tries, cr_tries;
>> uint32_t DP = intel_dp->DP;
>> uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>>
>> /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
>> - if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
>> + if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
>
> CHV has pattern 3.
Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
should abstract the check from intel_dp_max_link_bw.
Jani.
>
>> training_pattern = DP_TRAINING_PATTERN_3;
>>
>> /* channel equalization */
>> --
>> 1.9.3
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
2014-10-29 8:23 ` Jani Nikula
@ 2014-10-29 8:40 ` Ville Syrjälä
2014-10-29 9:07 ` Jani Nikula
0 siblings, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2014-10-29 8:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
> On Wed, 29 Oct 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> >> From: Dave Airlie <airlied@redhat.com>
> >>
> >> Ivybridge + 30" monitor prints a drm error on every modeset, since
> >> IVB doesn't support DP3 we should even bother trying to use it.
> >>
> >> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
> >> Signed-off-by: Dave Airlie <airlied@redhat.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> >> 1 file changed, 3 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> index f6a3fdd..87cfb92 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >> void
> >> intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >> {
> >> + struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> >> + struct drm_device *dev = encoder->dev;
> >> bool channel_eq = false;
> >> int tries, cr_tries;
> >> uint32_t DP = intel_dp->DP;
> >> uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> >>
> >> /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> >> - if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> >> + if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
> >
> > CHV has pattern 3.
>
> Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
> should abstract the check from intel_dp_max_link_bw.
Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.
>
> Jani.
>
>
> >
> >> training_pattern = DP_TRAINING_PATTERN_3;
> >>
> >> /* channel equalization */
> >> --
> >> 1.9.3
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
2014-10-29 8:40 ` [Intel-gfx] " Ville Syrjälä
@ 2014-10-29 9:07 ` Jani Nikula
2014-10-30 21:16 ` Jesse Barnes
0 siblings, 1 reply; 8+ messages in thread
From: Jani Nikula @ 2014-10-29 9:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Wed, 29 Oct 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
>> On Wed, 29 Oct 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
>> >> From: Dave Airlie <airlied@redhat.com>
>> >>
>> >> Ivybridge + 30" monitor prints a drm error on every modeset, since
>> >> IVB doesn't support DP3 we should even bother trying to use it.
>> >>
>> >> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
>> >> Signed-off-by: Dave Airlie <airlied@redhat.com>
>> >> ---
>> >> drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>> >> 1 file changed, 3 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> >> index f6a3fdd..87cfb92 100644
>> >> --- a/drivers/gpu/drm/i915/intel_dp.c
>> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> >> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>> >> void
>> >> intel_dp_complete_link_train(struct intel_dp *intel_dp)
>> >> {
>> >> + struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
>> >> + struct drm_device *dev = encoder->dev;
>> >> bool channel_eq = false;
>> >> int tries, cr_tries;
>> >> uint32_t DP = intel_dp->DP;
>> >> uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>> >>
>> >> /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
>> >> - if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
>> >> + if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
>> >
>> > CHV has pattern 3.
>>
>> Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
>> should abstract the check from intel_dp_max_link_bw.
>
> Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.
How about [1] instead? I forgot --in-reply-to, sorry.
BR,
Jani.
[1] http://mid.gmane.org/1414573406-17071-1-git-send-email-jani.nikula@intel.com
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell
2014-10-29 9:07 ` Jani Nikula
@ 2014-10-30 21:16 ` Jesse Barnes
0 siblings, 0 replies; 8+ messages in thread
From: Jesse Barnes @ 2014-10-30 21:16 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Wed, 29 Oct 2014 11:07:32 +0200
Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 29 Oct 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
> >> On Wed, 29 Oct 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> >> >> From: Dave Airlie <airlied@redhat.com>
> >> >>
> >> >> Ivybridge + 30" monitor prints a drm error on every modeset, since
> >> >> IVB doesn't support DP3 we should even bother trying to use it.
> >> >>
> >> >> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (on irc)
> >> >> Signed-off-by: Dave Airlie <airlied@redhat.com>
> >> >> ---
> >> >> drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> >> >> 1 file changed, 3 insertions(+), 1 deletion(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> >> index f6a3fdd..87cfb92 100644
> >> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> >> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >> >> void
> >> >> intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >> >> {
> >> >> + struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> >> >> + struct drm_device *dev = encoder->dev;
> >> >> bool channel_eq = false;
> >> >> int tries, cr_tries;
> >> >> uint32_t DP = intel_dp->DP;
> >> >> uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> >> >>
> >> >> /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> >> >> - if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> >> >> + if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
> >> >
> >> > CHV has pattern 3.
> >>
> >> Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
> >> should abstract the check from intel_dp_max_link_bw.
> >
> > Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.
>
> How about [1] instead? I forgot --in-reply-to, sorry.
>
> BR,
> Jani.
>
>
> [1] http://mid.gmane.org/1414573406-17071-1-git-send-email-jani.nikula@intel.com
Looks like we need something like that at least, assuming we're not
hitting the link_bw == DP_LINK_BW_5_4 case.
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
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2014-10-29 7:02 [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell Dave Airlie
2014-10-29 7:40 ` [Intel-gfx] " Daniel Vetter
2014-10-29 8:15 ` Ville Syrjälä
2014-10-29 8:22 ` [Intel-gfx] " Ville Syrjälä
2014-10-29 8:23 ` Jani Nikula
2014-10-29 8:40 ` [Intel-gfx] " Ville Syrjälä
2014-10-29 9:07 ` Jani Nikula
2014-10-30 21:16 ` Jesse Barnes
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