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d="scan'208";a="53991449" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.246.185]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2024 08:56:17 -0700 From: Jani Nikula To: Suraj Kandpal , intel-gfx@lists.freedesktop.org Cc: chaitanya.kumar.borah@intel.com, uma.shankar@intel.com, ankit.k.nautiyal@intel.com, Suraj Kandpal Subject: Re: [PATCH] drm/i915/pps: Disable DPLS_GATING around pps sequence In-Reply-To: <20240416093730.625486-2-suraj.kandpal@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20240416093730.625486-2-suraj.kandpal@intel.com> Date: Mon, 29 Jul 2024 18:56:14 +0300 Message-ID: <87msm0xkdd.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 16 Apr 2024, Suraj Kandpal wrote: > Disable bit 29 of SCLKGATE_DIS register around pps sequence > when we turn panel power on. > > --v2 > -Squash two commit together [Jani] > -Use IS_DISPLAY_VER [Jani] > -Fix multiline comment [Jani] > > Bspec: 49304 > Signed-off-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/display/intel_pps.c | 12 ++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c > index 3078dfac7817..2b2cead22a7d 100644 > --- a/drivers/gpu/drm/i915/display/intel_pps.c > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > @@ -948,6 +948,14 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp) > intel_de_posting_read(dev_priv, pp_ctrl_reg); > } > > + /* > + * WA: 16023567976 > + * Disable DPLS gating around power sequence. > + */ > + if (IS_DISPLAY_VER(dev_priv, 12, 14)) > + intel_de_rmw(dev_priv, SCLKGATE_DIS, > + DPLS_GATING_DISABLE, 1); > + > pp |= PANEL_POWER_ON; > if (!IS_IRONLAKE(dev_priv)) > pp |= PANEL_POWER_RESET; > @@ -958,6 +966,10 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp) > wait_panel_on(intel_dp); > intel_dp->pps.last_power_on = jiffies; > > + if (IS_DISPLAY_VER(dev_priv, 12, 14)) > + intel_de_rmw(dev_priv, SCLKGATE_DIS, > + DPLS_GATING_DISABLE, 0); > + > if (IS_IRONLAKE(dev_priv)) { > pp |= PANEL_POWER_RESET; /* restore panel reset bit */ > intel_de_write(dev_priv, pp_ctrl_reg, pp); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3f34efcd7d6c..1c2cd6cc254f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6250,6 +6250,10 @@ enum skl_power_gate { > #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) > #define SFUSE_STRAP_DDID_DETECTED (1 << 0) > > +/* SCLKGATE_DIS */ How is that comment helpful? Can we find another file under display/ for this register? BR, Jani. > +#define SCLKGATE_DIS _MMIO(0xc2020) > +#define DPLS_GATING_DISABLE REG_BIT(29) > + > #define WM_MISC _MMIO(0x45260) > #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) -- Jani Nikula, Intel