From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH] drm/i915/cnl: WaDisableI2mCycleOnWRPort
Date: Wed, 30 Aug 2017 11:45:42 +0300 [thread overview]
Message-ID: <87mv6h4f61.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20170829230751.21047-1-rodrigo.vivi@intel.com>
Rodrigo Vivi <rodrigo.vivi@intel.com> writes:
> On CNL B0 stepping GAM is not able to detect some deadlock
> condition and then rise the rise the gam_coh_flush.
>
> WA database and spec both mentions to set 4AB8[24]=1 as
> workaround. Alghouth register offset 0x4AB8 is not
s/Alghouth/Although
> documented for any platform.
>
References: HSD#1945815, BSID#1112
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..bbacdac5c794 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2373,6 +2373,7 @@ enum i915_power_well_id {
>
> #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
> #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
> +#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
>
> #if 0
> #define PRB0_TAIL _MMIO(0x2030)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a6ac9d0a4156..f087eb6b0134 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> + /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
> + if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
> + WA_SET_BIT(GAMT_CHKN_BIT_REG,
> + GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
> +
> /* WaForceContextSaveRestoreNonCoherent:cnl */
> WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2017-08-30 8:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-29 23:07 [PATCH] drm/i915/cnl: WaDisableI2mCycleOnWRPort Rodrigo Vivi
2017-08-29 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-30 2:42 ` ✓ Fi.CI.IGT: " Patchwork
2017-08-30 8:45 ` Mika Kuoppala [this message]
2017-08-31 4:59 ` [PATCH] " Vivi, Rodrigo
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