From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 39/43] drm/i915: Add dev_priv->psr_mmio_base
Date: Wed, 21 Oct 2015 10:09:49 +0300 [thread overview]
Message-ID: <87mvvcy9xe.fsf@intel.com> (raw)
In-Reply-To: <1445349709-21371-1-git-send-email-ville.syrjala@linux.intel.com>
On Tue, 20 Oct 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
> under dev_priv, like we for DSI and GPIO for example.
>
> TODO: could probably move a bunch of this kind of stuff into the device
> info instead...
>
> v2: Drop the surious whitespace change (Jani)
Are you surious about that?
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Yes.
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 15 ++++++++-------
> drivers/gpu/drm/i915/intel_psr.c | 27 +++++++++++++++------------
> 4 files changed, 27 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c38f766..74b17b4 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2536,7 +2536,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> yesno(work_busy(&dev_priv->psr.work.work)));
>
> if (HAS_DDI(dev))
> - enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
> + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> else {
> for_each_pipe(dev_priv, pipe) {
> stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
> @@ -2558,7 +2558,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>
> /* CHV PSR has no kind of performance counter */
> if (HAS_DDI(dev)) {
> - psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
> + psrperf = I915_READ(EDP_PSR_PERF_CNT) &
> EDP_PSR_PERF_CNT_MASK;
>
> seq_printf(m, "Performance_Counter: %u\n", psrperf);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e79f239..71a496d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1744,6 +1744,8 @@ struct drm_i915_private {
> /* MMIO base address for MIPI regs */
> uint32_t mipi_mmio_base;
>
> + uint32_t psr_mmio_base;
> +
> wait_queue_head_t gmbus_wait_queue;
>
> struct pci_dev *bridge_dev;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7723ed3..ed90915 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3043,8 +3043,9 @@ enum skl_disp_power_wells {
> #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
>
> /* HSW+ eDP PSR registers */
> -#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
> -#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
> +#define HSW_EDP_PSR_BASE 0x64800
> +#define BDW_EDP_PSR_BASE 0x6f800
> +#define EDP_PSR_CTL (dev_priv->psr_mmio_base + 0)
> #define EDP_PSR_ENABLE (1<<31)
> #define BDW_PSR_SINGLE_FRAME (1<<30)
> #define EDP_PSR_LINK_STANDBY (1<<27)
> @@ -3067,10 +3068,10 @@ enum skl_disp_power_wells {
> #define EDP_PSR_TP1_TIME_0us (3<<4)
> #define EDP_PSR_IDLE_FRAME_SHIFT 0
>
> -#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA(dev, i) (EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
> +#define EDP_PSR_AUX_CTL (dev_priv->psr_mmio_base + 0x10)
> +#define EDP_PSR_AUX_DATA(i) (dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
>
> -#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
> +#define EDP_PSR_STATUS_CTL (dev_priv->psr_mmio_base + 0x40)
> #define EDP_PSR_STATUS_STATE_MASK (7<<29)
> #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
> #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
> @@ -3094,10 +3095,10 @@ enum skl_disp_power_wells {
> #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
> #define EDP_PSR_STATUS_IDLE_MASK 0xf
>
> -#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
> +#define EDP_PSR_PERF_CNT (dev_priv->psr_mmio_base + 0x44)
> #define EDP_PSR_PERF_CNT_MASK 0xffffff
>
> -#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
> +#define EDP_PSR_DEBUG_CTL (dev_priv->psr_mmio_base + 0x60)
> #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
> #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
> #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index ff66718..3c973c5 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -183,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> DP_AUX_FRAME_SYNC_ENABLE);
>
> aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> - DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
> + DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
> aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> - DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
> + DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
>
> /* Setup AUX registers */
> for (i = 0; i < sizeof(aux_msg); i += 4)
> @@ -277,7 +277,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> idle_frames += 4;
> }
>
> - I915_WRITE(EDP_PSR_CTL(dev), val |
> + I915_WRITE(EDP_PSR_CTL, val |
> (IS_BROADWELL(dev) ? 0 : link_entry_time) |
> max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
> idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
> @@ -341,7 +341,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> + WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> WARN_ON(dev_priv->psr.active);
> lockdep_assert_held(&dev_priv->psr.lock);
>
> @@ -405,7 +405,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> }
>
> /* Avoid continuous PSR exit by masking memup and hpd */
> - I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
> + I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
> EDP_PSR_DEBUG_MASK_HPD);
>
> /* Enable PSR on the panel */
> @@ -467,17 +467,17 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> if (dev_priv->psr.active) {
> - I915_WRITE(EDP_PSR_CTL(dev),
> - I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
> + I915_WRITE(EDP_PSR_CTL,
> + I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
>
> /* Wait till PSR is idle */
> - if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
> + if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
> EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
> DRM_ERROR("Timed out waiting for PSR Idle State\n");
>
> dev_priv->psr.active = false;
> } else {
> - WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> + WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> }
> }
>
> @@ -524,7 +524,7 @@ static void intel_psr_work(struct work_struct *work)
> * and be ready for re-enable.
> */
> if (HAS_DDI(dev_priv->dev)) {
> - if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
> + if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
> EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
> DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
> return;
> @@ -567,11 +567,11 @@ static void intel_psr_exit(struct drm_device *dev)
> return;
>
> if (HAS_DDI(dev)) {
> - val = I915_READ(EDP_PSR_CTL(dev));
> + val = I915_READ(EDP_PSR_CTL);
>
> WARN_ON(!(val & EDP_PSR_ENABLE));
>
> - I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
> + I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
> } else {
> val = I915_READ(VLV_PSRCTL(pipe));
>
> @@ -752,6 +752,9 @@ void intel_psr_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
> + HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
> +
> INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
> mutex_init(&dev_priv->psr.lock);
> }
> --
> 2.4.9
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-10-21 7:06 UTC|newest]
Thread overview: 136+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-18 17:03 [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work ville.syrjala
2015-09-18 17:03 ` [PATCH 01/43] drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc, i2c}_bus() ville.syrjala
2015-09-21 7:34 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 02/43] drm/i915: Parametrize LRC registers ville.syrjala
2015-09-21 7:36 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 03/43] drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS ville.syrjala
2015-09-21 7:37 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 04/43] drm/i915: Parametrize fence registers ville.syrjala
2015-09-21 7:45 ` Jani Nikula
2015-09-21 12:33 ` Ville Syrjälä
2015-09-21 13:07 ` Ville Syrjälä
2015-09-21 15:05 ` [PATCH v2 " ville.syrjala
2015-09-25 12:02 ` Jani Nikula
2015-09-28 8:31 ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 05/43] drm/i915: Parametrize FBC_TAG registers ville.syrjala
2015-09-21 7:46 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 06/43] drm/i915: Parametrize ILK turbo registers ville.syrjala
2015-09-21 7:47 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 07/43] drm/i915: Replace raw numbers with the approproate register name in ILK turbo code ville.syrjala
2015-09-21 7:48 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 08/43] drm/i915: Parametrize TV luma/chroma filter registers ville.syrjala
2015-09-21 7:50 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 09/43] drm/i915: Parametrize DDI_BUF_TRANS registers ville.syrjala
2015-09-21 7:59 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 10/43] drm/i915: Parametrize CSR_PROGRAM registers ville.syrjala
2015-09-23 14:15 ` Mika Kuoppala
2015-09-23 15:17 ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 11/43] drm/i915: Parametrize UOS_RSA_SCRATCH ville.syrjala
2015-09-28 11:39 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 12/43] drm/i915: Add LO/HI PRIVATE_PAT registers ville.syrjala
2015-09-28 11:40 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 13/43] drm/i915: Always use GEN8_RING_PDP_{LDW, UDW} instead of hand rolling the register offsets ville.syrjala
2015-09-28 11:42 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 14/43] drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR ville.syrjala
2015-09-28 11:44 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 15/43] drm/i915: Parametrize PALETTE and LGC_PALETTE ville.syrjala
2015-09-28 11:45 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/ ville.syrjala
2015-09-22 16:47 ` [PATCH v2 " ville.syrjala
2015-09-28 11:50 ` Jani Nikula
2015-09-28 13:35 ` Daniel Vetter
2015-09-28 11:49 ` [PATCH " Jani Nikula
2015-09-18 17:03 ` [PATCH 17/43] drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/ ville.syrjala
2015-09-29 14:14 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 18/43] drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/ ville.syrjala
2015-09-29 14:16 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc ville.syrjala
2015-09-30 13:44 ` Jani Nikula
2015-09-30 13:53 ` Ville Syrjälä
2015-09-30 14:06 ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL() ville.syrjala
2015-09-30 13:58 ` Jani Nikula
2015-09-30 14:00 ` Ville Syrjälä
2015-10-26 14:49 ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 21/43] drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE ville.syrjala
2015-09-28 11:53 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/ ville.syrjala
2015-09-28 11:53 ` Jani Nikula
2015-09-28 13:38 ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 23/43] drm/i915: Eliminate weird parameter inversion from BXT PPS registers ville.syrjala
2015-10-12 16:41 ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 24/43] drm/i915: Parametrize HSW video DIP data registers ville.syrjala
2015-10-12 15:54 ` Jesse Barnes
2015-10-12 16:15 ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines ville.syrjala
2015-10-12 15:56 ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 26/43] drm/i915: Protect register macro arguments ville.syrjala
2015-10-12 16:03 ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 27/43] drm/i915: Fix a few bad hex numbers in register defines ville.syrjala
2015-10-12 16:04 ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 28/43] drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function ville.syrjala
2015-10-12 16:05 ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 29/43] drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc ville.syrjala
2015-10-12 16:06 ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 30/43] drm/i915: Parametrize and fix SWF registers ville.syrjala
2015-10-12 16:07 ` Jesse Barnes
2015-10-12 16:17 ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 31/43] drm/i915: Throw out some useless variables ville.syrjala
2015-09-22 16:50 ` [PATCH v2 " ville.syrjala
2015-10-12 16:09 ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 32/43] drm/i915: Clean up LVDS register handling ville.syrjala
2015-10-12 16:09 ` Jesse Barnes
2015-11-01 15:33 ` Lukas Wunner
2015-11-04 16:59 ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE ville.syrjala
2015-10-12 16:12 ` Jesse Barnes
2015-10-13 11:21 ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 34/43] drm/i915: Turn __raw_i915_read8() & co. in to inline functions ville.syrjala
2015-09-18 17:03 ` [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h ville.syrjala
2015-09-18 17:42 ` Chris Wilson
2015-09-18 18:23 ` Ville Syrjälä
2015-09-18 18:33 ` Chris Wilson
2015-09-18 18:37 ` Ville Syrjälä
2015-09-18 18:44 ` Chris Wilson
2015-09-18 19:26 ` Ville Syrjälä
2015-09-21 16:26 ` Jesse Barnes
2015-09-21 16:53 ` Ville Syrjälä
2015-09-21 16:57 ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 36/43] drm/i915: Remove the magic AUX_CTL is at DP + foo tricks ville.syrjala
2015-09-18 17:03 ` [PATCH 37/43] drm/i915: Replace the aux ddc name switch statement with a table ville.syrjala
2015-09-18 17:03 ` [PATCH 38/43] drm/i915: Parametrize AUX registes ville.syrjala
2015-09-28 12:15 ` Jani Nikula
2015-09-28 13:28 ` Daniel Vetter
2015-09-28 13:34 ` Ville Syrjälä
2015-09-28 13:52 ` Daniel Vetter
2015-09-28 13:57 ` Jani Nikula
2015-09-28 15:09 ` [PATCH v2 38/43] drm/i915: Parametrize AUX registers ville.syrjala
2015-10-20 13:05 ` Jani Nikula
2015-10-20 13:37 ` Ville Syrjälä
2015-10-20 14:00 ` [PATCH v3 " ville.syrjala
2015-10-21 7:08 ` Jani Nikula
2015-09-18 17:03 ` [PATCH 39/43] drm/i915: Add dev_priv->psr_mmio_base ville.syrjala
2015-10-20 13:08 ` Jani Nikula
2015-10-20 14:01 ` [PATCH v2 " ville.syrjala
2015-10-21 7:09 ` Jani Nikula [this message]
2015-09-18 17:03 ` [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[] ville.syrjala
2015-09-28 12:28 ` Jani Nikula
2015-09-28 14:36 ` Ville Syrjälä
2015-09-28 15:10 ` [PATCH v2 " ville.syrjala
2015-10-20 14:02 ` [PATCH v3 " ville.syrjala
2015-09-18 17:03 ` [PATCH 41/43] drm/i915: Model PSR AUX register selection more like the normal AUX code ville.syrjala
2015-09-28 15:11 ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 42/43] drm/i915: Prefix raw register defines with underscore ville.syrjala
2015-09-18 17:03 ` [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write ville.syrjala
2015-09-18 17:33 ` Chris Wilson
2015-09-18 17:43 ` Ville Syrjälä
2015-09-18 18:12 ` Chris Wilson
2015-09-18 18:34 ` Ville Syrjälä
2015-09-23 15:23 ` Daniel Vetter
2015-09-24 15:38 ` Ville Syrjälä
2015-09-28 12:56 ` Jani Nikula
2015-09-28 13:03 ` Ville Syrjälä
2015-09-28 13:52 ` Daniel Vetter
2015-09-18 18:17 ` [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work Chris Wilson
2015-09-22 17:41 ` Ville Syrjälä
2015-10-28 12:55 ` Jani Nikula
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