* [PATCH v2 01/10] drm/i915/gen8: Add gen8_init_workarounds for common WA
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 02/10] drm/i915/gen8: Move INSTPM WA to common function Arun Siluvery
` (8 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
WA in this function should be ordered based on register address.
The following order is suggested (Ville),
instpm
mi_mode
row chicken
half slice chicken
common slice chicken
hdc chicken
cache_mode_0
cache_mode_1
gt_mode
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 16a4ead..10f9ea0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -800,11 +800,22 @@ static int wa_add(struct drm_i915_private *dev_priv,
#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
+static int gen8_init_workarounds(struct intel_engine_cs *ring)
+{
+
+ return 0;
+}
+
static int bdw_init_workarounds(struct intel_engine_cs *ring)
{
+ int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ ret = gen8_init_workarounds(ring);
+ if (ret)
+ return ret;
+
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
/* WaDisableAsyncFlipPerfMode:bdw */
@@ -868,9 +879,14 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
static int chv_init_workarounds(struct intel_engine_cs *ring)
{
+ int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ ret = gen8_init_workarounds(ring);
+ if (ret)
+ return ret;
+
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
/* WaDisableAsyncFlipPerfMode:chv */
--
1.9.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 02/10] drm/i915/gen8: Move INSTPM WA to common function
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 01/10] drm/i915/gen8: Add gen8_init_workarounds for common WA Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 03/10] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn Arun Siluvery
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 10f9ea0..4f3942f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -802,6 +802,10 @@ static int wa_add(struct drm_i915_private *dev_priv,
static int gen8_init_workarounds(struct intel_engine_cs *ring)
{
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
return 0;
}
@@ -816,8 +820,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
if (ret)
return ret;
- WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
/* WaDisableAsyncFlipPerfMode:bdw */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
@@ -887,8 +889,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
if (ret)
return ret;
- WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
/* WaDisableAsyncFlipPerfMode:chv */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
--
1.9.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 03/10] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 01/10] drm/i915/gen8: Add gen8_init_workarounds for common WA Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 02/10] drm/i915/gen8: Move INSTPM WA to common function Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 04/10] drm/i915/gen8: Move WaDisablePartialInstShootdown " Arun Siluvery
` (6 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4f3942f..3bc14fa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -807,6 +807,9 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
+ /* WaDisableAsyncFlipPerfMode:bdw,chv */
+ WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+
return 0;
}
@@ -820,9 +823,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
if (ret)
return ret;
- /* WaDisableAsyncFlipPerfMode:bdw */
- WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
/* WaDisablePartialInstShootdown:bdw */
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -889,9 +889,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
if (ret)
return ret;
- /* WaDisableAsyncFlipPerfMode:chv */
- WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
/* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
--
1.9.1
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 04/10] drm/i915/gen8: Move WaDisablePartialInstShootdown to common init fn
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
` (2 preceding siblings ...)
2015-09-25 16:40 ` [PATCH v2 03/10] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating Arun Siluvery
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3bc14fa..d8fa9d1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -810,6 +810,10 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableAsyncFlipPerfMode:bdw,chv */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+ /* WaDisablePartialInstShootdown:bdw,chv */
+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+ PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+
return 0;
}
@@ -823,11 +827,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
if (ret)
return ret;
- /* WaDisablePartialInstShootdown:bdw */
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
- STALL_DOP_GATING_DISABLE);
+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* WaDisableDopClockGating:bdw */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
@@ -889,11 +890,8 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
if (ret)
return ret;
- /* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
- STALL_DOP_GATING_DISABLE);
+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* Use Force Non-Coherent whenever executing a 3D context. This is a
* workaround for a possible hang in the unlikely event a TLB
--
1.9.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
` (3 preceding siblings ...)
2015-09-25 16:40 ` [PATCH v2 04/10] drm/i915/gen8: Move WaDisablePartialInstShootdown " Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-28 8:44 ` Jani Nikula
2015-09-25 16:40 ` [PATCH v2 06/10] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn Arun Siluvery
` (4 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Dropping it because it is for pre-production stepping.
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d8fa9d1..0b545cf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -827,9 +827,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
if (ret)
return ret;
- /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
-
/* WaDisableDopClockGating:bdw */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
DOP_CLOCK_GATING_DISABLE);
--
1.9.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating
2015-09-25 16:40 ` [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating Arun Siluvery
@ 2015-09-28 8:44 ` Jani Nikula
2015-09-28 9:51 ` Arun Siluvery
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2015-09-28 8:44 UTC (permalink / raw)
To: Arun Siluvery, intel-gfx
On Fri, 25 Sep 2015, Arun Siluvery <arun.siluvery@linux.intel.com> wrote:
> Dropping it because it is for pre-production stepping.
Hum, why have we added a pre-pro w/a without a stepping check... should
we backport this to stable kernels? What's the impact on production
hardware with vs. without the w/a?
BR,
Jani.
>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d8fa9d1..0b545cf 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -827,9 +827,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> if (ret)
> return ret;
>
> - /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> - WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
> -
> /* WaDisableDopClockGating:bdw */
> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating
2015-09-28 8:44 ` Jani Nikula
@ 2015-09-28 9:51 ` Arun Siluvery
2015-09-28 14:06 ` Daniel Vetter
0 siblings, 1 reply; 16+ messages in thread
From: Arun Siluvery @ 2015-09-28 9:51 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 28/09/2015 09:44, Jani Nikula wrote:
> On Fri, 25 Sep 2015, Arun Siluvery <arun.siluvery@linux.intel.com> wrote:
>> Dropping it because it is for pre-production stepping.
>
> Hum, why have we added a pre-pro w/a without a stepping check... should
> we backport this to stable kernels? What's the impact on production
> hardware with vs. without the w/a?
The original patch that added pre-production comment is very old.
commit 101b376d358e2f724db5e0ac4d207079b16c4754
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Thu Oct 9 07:11:47 2014 -0700
drm/i915/bdw: Remove BDW preproduction W/As until C stepping.
Let's clean this a bit
v2: Rebase after other Mika's patch that removed some BDW
production workarounds.
v3: Removed stepping info.
For BDW it is only applicable UNTIL_D0. According to hsd it is related
to a hang in emulation but I am checking with HW team to understand its
impact (if any) better in production steppings.
regards
Arun
>
> BR,
> Jani.
>
>
>>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
>> 1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index d8fa9d1..0b545cf 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -827,9 +827,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>> if (ret)
>> return ret;
>>
>> - /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
>> - WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
>> -
>> /* WaDisableDopClockGating:bdw */
>> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>> DOP_CLOCK_GATING_DISABLE);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
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^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating
2015-09-28 9:51 ` Arun Siluvery
@ 2015-09-28 14:06 ` Daniel Vetter
0 siblings, 0 replies; 16+ messages in thread
From: Daniel Vetter @ 2015-09-28 14:06 UTC (permalink / raw)
To: Arun Siluvery; +Cc: intel-gfx
On Mon, Sep 28, 2015 at 10:51:39AM +0100, Arun Siluvery wrote:
> On 28/09/2015 09:44, Jani Nikula wrote:
> >On Fri, 25 Sep 2015, Arun Siluvery <arun.siluvery@linux.intel.com> wrote:
> >>Dropping it because it is for pre-production stepping.
> >
> >Hum, why have we added a pre-pro w/a without a stepping check... should
> >we backport this to stable kernels? What's the impact on production
> >hardware with vs. without the w/a?
>
> The original patch that added pre-production comment is very old.
>
> commit 101b376d358e2f724db5e0ac4d207079b16c4754
> Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Date: Thu Oct 9 07:11:47 2014 -0700
>
> drm/i915/bdw: Remove BDW preproduction W/As until C stepping.
>
> Let's clean this a bit
>
> v2: Rebase after other Mika's patch that removed some BDW production
> workarounds.
> v3: Removed stepping info.
This commit also changed the wa right below by dropping the "May not be
needed for production.", but did not add a "(pre-production)" instead for
that case. And we're keeping that one. Would definitely be good to check
what's up with those two. I'll hold of merging this patch for now.
-Daniel
>
>
> For BDW it is only applicable UNTIL_D0. According to hsd it is related to a
> hang in emulation but I am checking with HW team to understand its impact
> (if any) better in production steppings.
>
> regards
> Arun
>
> >
> >BR,
> >Jani.
> >
> >
> >>
> >>Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> >>---
> >> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
> >> 1 file changed, 3 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>index d8fa9d1..0b545cf 100644
> >>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>@@ -827,9 +827,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> >> if (ret)
> >> return ret;
> >>
> >>- /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> >>- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
> >>-
> >> /* WaDisableDopClockGating:bdw */
> >> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> >> DOP_CLOCK_GATING_DISABLE);
> >>--
> >>1.9.1
> >>
> >>_______________________________________________
> >>Intel-gfx mailing list
> >>Intel-gfx@lists.freedesktop.org
> >>http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 06/10] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
` (4 preceding siblings ...)
2015-09-25 16:40 ` [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 07/10] drm/i915/gen8: Move Wa4x4STCOptimizationDisable " Arun Siluvery
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0b545cf..a42dff9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -814,6 +814,16 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+ /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
+ * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
+ * polygons in the same 8x4 pixel/sample area to be processed without
+ * stalling waiting for the earlier ones to write to Hierarchical Z
+ * buffer."
+ *
+ * This optimization is off by default for BDW and CHV; turn it on.
+ */
+ WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
+
return 0;
}
@@ -848,16 +858,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
- /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
- * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
- * polygons in the same 8x4 pixel/sample area to be processed without
- * stalling waiting for the earlier ones to write to Hierarchical Z
- * buffer."
- *
- * This optimization is off by default for Broadwell; turn it on.
- */
- WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
/* Wa4x4STCOptimizationDisable:bdw */
WA_SET_BIT_MASKED(CACHE_MODE_1,
GEN8_4x4_STC_OPTIMIZATION_DISABLE);
@@ -900,11 +900,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
HDC_FORCE_NON_COHERENT |
HDC_DONOT_FETCH_MEM_WHEN_MASKED);
- /* According to the CACHE_MODE_0 default value documentation, some
- * CHV platforms disable this optimization by default. Turn it on.
- */
- WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
/* Wa4x4STCOptimizationDisable:chv */
WA_SET_BIT_MASKED(CACHE_MODE_1,
GEN8_4x4_STC_OPTIMIZATION_DISABLE);
--
1.9.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 07/10] drm/i915/gen8: Move Wa4x4STCOptimizationDisable to common init fn
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
` (5 preceding siblings ...)
2015-09-25 16:40 ` [PATCH v2 06/10] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 08/10] drm/i915/gen8: Move GEN7_GT_MODE WA " Arun Siluvery
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a42dff9..1b12584 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -824,6 +824,9 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
*/
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
+ /* Wa4x4STCOptimizationDisable:bdw,chv */
+ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+
return 0;
}
@@ -858,10 +861,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
- /* Wa4x4STCOptimizationDisable:bdw */
- WA_SET_BIT_MASKED(CACHE_MODE_1,
- GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
/*
* BSpec recommends 8x4 when MSAA is used,
* however in practice 16x4 seems fastest.
@@ -900,10 +899,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
HDC_FORCE_NON_COHERENT |
HDC_DONOT_FETCH_MEM_WHEN_MASKED);
- /* Wa4x4STCOptimizationDisable:chv */
- WA_SET_BIT_MASKED(CACHE_MODE_1,
- GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
--
1.9.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 08/10] drm/i915/gen8: Move GEN7_GT_MODE WA to common init fn
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
` (6 preceding siblings ...)
2015-09-25 16:40 ` [PATCH v2 07/10] drm/i915/gen8: Move Wa4x4STCOptimizationDisable " Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 09/10] drm/i915/gen8: Move WaForceEnableNonCoherent " Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked " Arun Siluvery
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++++++++++----------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1b12584..97f9cec 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -827,6 +827,18 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
/* Wa4x4STCOptimizationDisable:bdw,chv */
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+ /*
+ * BSpec recommends 8x4 when MSAA is used,
+ * however in practice 16x4 seems fastest.
+ *
+ * Note that PS/WM thread counts depend on the WIZ hashing
+ * disable bit, which we don't touch here, but it's good
+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+ */
+ WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+ GEN6_WIZ_HASHING_MASK,
+ GEN6_WIZ_HASHING_16x4);
+
return 0;
}
@@ -861,18 +873,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
- /*
- * BSpec recommends 8x4 when MSAA is used,
- * however in practice 16x4 seems fastest.
- *
- * Note that PS/WM thread counts depend on the WIZ hashing
- * disable bit, which we don't touch here, but it's good
- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
- */
- WA_SET_FIELD_MASKED(GEN7_GT_MODE,
- GEN6_WIZ_HASHING_MASK,
- GEN6_WIZ_HASHING_16x4);
-
return 0;
}
@@ -902,18 +902,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
- /*
- * BSpec recommends 8x4 when MSAA is used,
- * however in practice 16x4 seems fastest.
- *
- * Note that PS/WM thread counts depend on the WIZ hashing
- * disable bit, which we don't touch here, but it's good
- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
- */
- WA_SET_FIELD_MASKED(GEN7_GT_MODE,
- GEN6_WIZ_HASHING_MASK,
- GEN6_WIZ_HASHING_16x4);
-
return 0;
}
--
1.9.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 09/10] drm/i915/gen8: Move WaForceEnableNonCoherent to common init fn
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
` (7 preceding siblings ...)
2015-09-25 16:40 ` [PATCH v2 08/10] drm/i915/gen8: Move GEN7_GT_MODE WA " Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:40 ` [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked " Arun Siluvery
9 siblings, 0 replies; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 97f9cec..1e60aa0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -814,6 +814,14 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+ /* Use Force Non-Coherent whenever executing a 3D context. This is a
+ * workaround for for a possible hang in the unlikely event a TLB
+ * invalidation occurs during a PSD flush.
+ */
+ /* WaForceEnableNonCoherent:bdw,chv */
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_NON_COHERENT);
+
/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
* polygons in the same 8x4 pixel/sample area to be processed without
@@ -859,13 +867,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
- /* Use Force Non-Coherent whenever executing a 3D context. This is a
- * workaround for for a possible hang in the unlikely event a TLB
- * invalidation occurs during a PSD flush.
- */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
- /* WaForceEnableNonCoherent:bdw */
- HDC_FORCE_NON_COHERENT |
/* WaForceContextSaveRestoreNonCoherent:bdw */
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
/* WaHdcDisableFetchWhenMasked:bdw */
@@ -889,14 +891,8 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
- /* Use Force Non-Coherent whenever executing a 3D context. This is a
- * workaround for a possible hang in the unlikely event a TLB
- * invalidation occurs during a PSD flush.
- */
- /* WaForceEnableNonCoherent:chv */
/* WaHdcDisableFetchWhenMasked:chv */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FORCE_NON_COHERENT |
HDC_DONOT_FETCH_MEM_WHEN_MASKED);
/* Improve HiZ throughput on CHV. */
--
1.9.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn
2015-09-25 16:40 [PATCH v2 00/10] Gen8 WA cleanup patches Arun Siluvery
` (8 preceding siblings ...)
2015-09-25 16:40 ` [PATCH v2 09/10] drm/i915/gen8: Move WaForceEnableNonCoherent " Arun Siluvery
@ 2015-09-25 16:40 ` Arun Siluvery
2015-09-25 16:54 ` Ville Syrjälä
9 siblings, 1 reply; 16+ messages in thread
From: Arun Siluvery @ 2015-09-25 16:40 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1e60aa0..35afe73 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -819,7 +819,9 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
* invalidation occurs during a PSD flush.
*/
/* WaForceEnableNonCoherent:bdw,chv */
+ /* WaHdcDisableFetchWhenMasked:bdw,chv */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_DONOT_FETCH_MEM_WHEN_MASKED |
HDC_FORCE_NON_COHERENT);
/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
@@ -870,8 +872,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(HDC_CHICKEN0,
/* WaForceContextSaveRestoreNonCoherent:bdw */
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
- /* WaHdcDisableFetchWhenMasked:bdw */
- HDC_DONOT_FETCH_MEM_WHEN_MASKED |
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
@@ -891,10 +891,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
- /* WaHdcDisableFetchWhenMasked:chv */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_DONOT_FETCH_MEM_WHEN_MASKED);
-
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
--
1.9.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn
2015-09-25 16:40 ` [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked " Arun Siluvery
@ 2015-09-25 16:54 ` Ville Syrjälä
2015-09-28 14:07 ` Daniel Vetter
0 siblings, 1 reply; 16+ messages in thread
From: Ville Syrjälä @ 2015-09-25 16:54 UTC (permalink / raw)
To: Arun Siluvery; +Cc: intel-gfx
On Fri, Sep 25, 2015 at 05:40:46PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Series lgtm, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1e60aa0..35afe73 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -819,7 +819,9 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
> * invalidation occurs during a PSD flush.
> */
> /* WaForceEnableNonCoherent:bdw,chv */
> + /* WaHdcDisableFetchWhenMasked:bdw,chv */
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> + HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> HDC_FORCE_NON_COHERENT);
>
> /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> @@ -870,8 +872,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> /* WaForceContextSaveRestoreNonCoherent:bdw */
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> - /* WaHdcDisableFetchWhenMasked:bdw */
> - HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
> (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>
> @@ -891,10 +891,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> /* WaDisableThreadStallDopClockGating:chv */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
>
> - /* WaHdcDisableFetchWhenMasked:chv */
> - WA_SET_BIT_MASKED(HDC_CHICKEN0,
> - HDC_DONOT_FETCH_MEM_WHEN_MASKED);
> -
> /* Improve HiZ throughput on CHV. */
> WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
>
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn
2015-09-25 16:54 ` Ville Syrjälä
@ 2015-09-28 14:07 ` Daniel Vetter
0 siblings, 0 replies; 16+ messages in thread
From: Daniel Vetter @ 2015-09-28 14:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Sep 25, 2015 at 07:54:46PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 05:40:46PM +0100, Arun Siluvery wrote:
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>
> Series lgtm, so
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Except for patch 5 all merged to dinq, thanks.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++------
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 1e60aa0..35afe73 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -819,7 +819,9 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
> > * invalidation occurs during a PSD flush.
> > */
> > /* WaForceEnableNonCoherent:bdw,chv */
> > + /* WaHdcDisableFetchWhenMasked:bdw,chv */
> > WA_SET_BIT_MASKED(HDC_CHICKEN0,
> > + HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> > HDC_FORCE_NON_COHERENT);
> >
> > /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> > @@ -870,8 +872,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> > WA_SET_BIT_MASKED(HDC_CHICKEN0,
> > /* WaForceContextSaveRestoreNonCoherent:bdw */
> > HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> > - /* WaHdcDisableFetchWhenMasked:bdw */
> > - HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> > /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
> > (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
> >
> > @@ -891,10 +891,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> > /* WaDisableThreadStallDopClockGating:chv */
> > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
> >
> > - /* WaHdcDisableFetchWhenMasked:chv */
> > - WA_SET_BIT_MASKED(HDC_CHICKEN0,
> > - HDC_DONOT_FETCH_MEM_WHEN_MASKED);
> > -
> > /* Improve HiZ throughput on CHV. */
> > WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
> >
> > --
> > 1.9.1
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 16+ messages in thread